1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
7 * Please note: there are two version of the board
8 * one with NAND and the other with eMMC.
9 * Both NAND and eMMC cannot be set because they share the
16 #include <asm/arch/clock.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/arch/mx6-ddr.h>
20 #include <asm/arch/iomux.h>
21 #include <asm/arch/mx6-pins.h>
22 #include <asm/mach-imx/iomux-v3.h>
23 #include <asm/mach-imx/boot_mode.h>
24 #include <asm/mach-imx/mxc_i2c.h>
25 #include <asm/mach-imx/spi.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
31 #include <fsl_esdhc_imx.h>
35 #include <asm/arch/sys_proto.h>
36 #include <asm/sections.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
45 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
46 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
51 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
54 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
56 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
58 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
60 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
64 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
66 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
67 #define USDHC1_CD_GPIO IMX_GPIO_NR(6, 31)
68 #define USER_LED IMX_GPIO_NR(1, 4)
69 #define IMX6Q_DRIVE_STRENGTH 0x30
73 gd->ram_size = imx_ddr_size();
77 void board_turn_off_led(void)
79 gpio_direction_output(USER_LED, 0);
82 static iomux_v3_cfg_t const uart1_pads[] = {
83 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
84 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
87 static iomux_v3_cfg_t const enet_pads[] = {
88 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
103 MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
106 static iomux_v3_cfg_t const ecspi1_pads[] = {
107 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
108 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
109 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
110 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
113 #ifdef CONFIG_CMD_NAND
115 static iomux_v3_cfg_t const nfc_pads[] = {
116 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
117 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
118 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
119 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
120 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
121 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
122 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
123 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
124 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
125 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
126 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
127 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
128 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
129 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
130 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
131 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
132 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
133 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
134 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
138 static struct i2c_pads_info i2c_pad_info2 = {
140 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
141 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
142 .gp = IMX_GPIO_NR(1, 5)
145 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
146 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
147 .gp = IMX_GPIO_NR(1, 6)
151 static struct fsl_esdhc_cfg usdhc_cfg[] = {
152 {.esdhc_base = USDHC1_BASE_ADDR,
154 #ifndef CONFIG_CMD_NAND
159 static iomux_v3_cfg_t const usdhc1_pads[] = {
160 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
166 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
169 #if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
170 static iomux_v3_cfg_t const usdhc4_pads[] = {
171 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
184 int board_mmc_get_env_dev(int devno)
189 int board_mmc_getcd(struct mmc *mmc)
191 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
194 switch (cfg->esdhc_base) {
195 case USDHC1_BASE_ADDR:
196 ret = !gpio_get_value(USDHC1_CD_GPIO);
198 case USDHC4_BASE_ADDR:
199 ret = 1; /* eMMC/uSDHC4 is always present */
206 int board_mmc_init(bd_t *bis)
208 #ifndef CONFIG_SPL_BUILD
212 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
215 imx_iomux_v3_setup_multiple_pads(
216 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
217 gpio_direction_input(USDHC1_CD_GPIO);
218 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
220 #ifndef CONFIG_CMD_NAND
222 imx_iomux_v3_setup_multiple_pads(
223 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
224 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
228 printf("Warning: you configured more USDHC controllers"
229 "(%d) then supported by the board (%d)\n",
230 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
234 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
241 struct src *psrc = (struct src *)SRC_BASE_ADDR;
242 unsigned reg = readl(&psrc->sbmr1) >> 11;
244 * Upon reading BOOT_CFG register the following map is done:
245 * Bit 11 and 12 of BOOT_CFG register can determine the current
254 imx_iomux_v3_setup_multiple_pads(
255 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
256 gpio_direction_input(USDHC1_CD_GPIO);
257 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
258 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
259 usdhc_cfg[0].max_bus_width = 4;
260 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
263 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
267 static void setup_iomux_uart(void)
269 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
272 static void setup_iomux_enet(void)
274 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
276 gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
278 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
282 static void setup_spi(void)
284 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
285 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
287 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
289 enable_spi_clk(true, 0);
292 #ifdef CONFIG_CMD_NAND
293 static void setup_gpmi_nand(void)
295 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
297 /* config gpmi nand iomux */
298 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
300 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
301 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
303 /* config gpmi and bch clock to 100 MHz */
304 clrsetbits_le32(&mxc_ccm->cs2cdr,
305 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
306 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
307 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
308 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
309 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
310 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
312 /* enable ENFC_CLK_ROOT clock */
313 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
315 /* enable gpmi and bch clock gating */
316 setbits_le32(&mxc_ccm->CCGR4,
317 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
318 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
319 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
320 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
321 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
323 /* enable apbh clock gating */
324 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
328 int board_spi_cs_gpio(unsigned bus, unsigned cs)
330 if (bus != 0 || (cs != 0))
333 return IMX_GPIO_NR(3, 19);
336 int board_eth_init(bd_t *bis)
340 return cpu_eth_init(bis);
343 int board_early_init_f(void)
352 /* address of boot parameters */
353 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
355 #ifdef CONFIG_SYS_I2C_MXC
356 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
359 #ifdef CONFIG_MXC_SPI
363 #ifdef CONFIG_CMD_NAND
370 #ifdef CONFIG_CMD_BMODE
372 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
373 * see Table 8-11 and Table 5-9
374 * BOOT_CFG1[7] = 1 (boot from NAND)
375 * BOOT_CFG1[5] = 0 - raw NAND
376 * BOOT_CFG1[4] = 0 - default pad settings
377 * BOOT_CFG1[3:2] = 00 - devices = 1
378 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
379 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
380 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
381 * BOOT_CFG2[0] = 0 - Reset time 12ms
383 static const struct boot_mode board_boot_modes[] = {
384 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
385 {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
386 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
391 int board_late_init(void)
393 #ifdef CONFIG_CMD_BMODE
394 add_board_boot_modes(board_boot_modes);
400 #ifdef CONFIG_SPL_BUILD
402 #include <linux/libfdt.h>
404 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
405 .dram_sdclk_0 = 0x00000030,
406 .dram_sdclk_1 = 0x00000030,
407 .dram_cas = 0x00000030,
408 .dram_ras = 0x00000030,
409 .dram_reset = 0x00000030,
410 .dram_sdcke0 = 0x00000030,
411 .dram_sdcke1 = 0x00000030,
412 .dram_sdba2 = 0x00000000,
413 .dram_sdodt0 = 0x00000030,
414 .dram_sdodt1 = 0x00000030,
415 .dram_sdqs0 = 0x00000030,
416 .dram_sdqs1 = 0x00000030,
417 .dram_sdqs2 = 0x00000030,
418 .dram_sdqs3 = 0x00000030,
419 .dram_sdqs4 = 0x00000030,
420 .dram_sdqs5 = 0x00000030,
421 .dram_sdqs6 = 0x00000030,
422 .dram_sdqs7 = 0x00000030,
423 .dram_dqm0 = 0x00000030,
424 .dram_dqm1 = 0x00000030,
425 .dram_dqm2 = 0x00000030,
426 .dram_dqm3 = 0x00000030,
427 .dram_dqm4 = 0x00000030,
428 .dram_dqm5 = 0x00000030,
429 .dram_dqm6 = 0x00000030,
430 .dram_dqm7 = 0x00000030,
433 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
434 .grp_ddr_type = 0x000C0000,
435 .grp_ddrmode_ctl = 0x00020000,
436 .grp_ddrpke = 0x00000000,
437 .grp_addds = IMX6Q_DRIVE_STRENGTH,
438 .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
439 .grp_ddrmode = 0x00020000,
440 .grp_b0ds = IMX6Q_DRIVE_STRENGTH,
441 .grp_b1ds = IMX6Q_DRIVE_STRENGTH,
442 .grp_b2ds = IMX6Q_DRIVE_STRENGTH,
443 .grp_b3ds = IMX6Q_DRIVE_STRENGTH,
444 .grp_b4ds = IMX6Q_DRIVE_STRENGTH,
445 .grp_b5ds = IMX6Q_DRIVE_STRENGTH,
446 .grp_b6ds = IMX6Q_DRIVE_STRENGTH,
447 .grp_b7ds = IMX6Q_DRIVE_STRENGTH,
450 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
451 .p0_mpwldectrl0 = 0x00140014,
452 .p0_mpwldectrl1 = 0x000A0015,
453 .p1_mpwldectrl0 = 0x000A001E,
454 .p1_mpwldectrl1 = 0x000A0015,
455 .p0_mpdgctrl0 = 0x43080314,
456 .p0_mpdgctrl1 = 0x02680300,
457 .p1_mpdgctrl0 = 0x430C0318,
458 .p1_mpdgctrl1 = 0x03000254,
459 .p0_mprddlctl = 0x3A323234,
460 .p1_mprddlctl = 0x3E3C3242,
461 .p0_mpwrdlctl = 0x2A2E3632,
462 .p1_mpwrdlctl = 0x3C323E34,
465 static struct mx6_ddr3_cfg mem_ddr = {
479 static void ccgr_init(void)
481 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
483 writel(0x00C03F3F, &ccm->CCGR0);
484 writel(0x0030FC03, &ccm->CCGR1);
485 writel(0x0FFFC000, &ccm->CCGR2);
486 writel(0x3FF00000, &ccm->CCGR3);
487 writel(0x00FFF300, &ccm->CCGR4);
488 writel(0x0F0000C3, &ccm->CCGR5);
489 writel(0x000003FF, &ccm->CCGR6);
492 static void spl_dram_init(void)
494 struct mx6_ddr_sysinfo sysinfo = {
495 /* width of data bus:0=16,1=32,2=64 */
497 /* config for full 4GB range so that get_mem_size() works */
498 .cs_density = 32, /* 32Gb per CS */
499 /* single chip select */
502 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
503 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
504 .walat = 1, /* Write additional latency */
505 .ralat = 5, /* Read additional latency */
506 .mif3_mode = 3, /* Command prediction working mode */
507 .bi_on = 1, /* Bank interleaving enabled */
508 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
509 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
510 .ddr_type = DDR_TYPE_DDR3,
511 .refsel = 1, /* Refresh cycles at 32KHz */
512 .refr = 7, /* 8 refresh commands per refresh cycle */
515 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
516 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
519 void board_boot_order(u32 *spl_boot_list)
521 spl_boot_list[0] = spl_boot_device();
522 printf("Boot device %x\n", spl_boot_list[0]);
523 switch (spl_boot_list[0]) {
524 case BOOT_DEVICE_SPI:
525 spl_boot_list[1] = BOOT_DEVICE_UART;
527 case BOOT_DEVICE_MMC1:
528 spl_boot_list[1] = BOOT_DEVICE_SPI;
529 spl_boot_list[2] = BOOT_DEVICE_UART;
532 printf("Boot device %x\n", spl_boot_list[0]);
536 void board_init_f(ulong dummy)
538 #ifdef CONFIG_CMD_NAND
543 /* setup clock gating */
546 /* setup AIPS and disable watchdog */
552 board_early_init_f();
559 /* UART clocks enabled and gd valid - init serial console */
560 preloader_console_init();
562 /* DDR initialization */
566 memset(__bss_start, 0, __bss_end - __bss_start);
568 /* load/boot image from boot device */
569 board_init_r(NULL, 0);