board/phytec/pcm052/pcm052.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
   5  *
   6  * Copyright 2013 Freescale Semiconductor, Inc.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux-vf610.h>
  13 #include <asm/arch/ddrmc-vf610.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <led.h>
  17 #include <environment.h>
  18 #include <miiphy.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 static struct ddrmc_cr_setting pcm052_cr_settings[] = {
  23         /* not in the datasheets, but in the original code */
  24         { 0x00002000, 105 },
  25         { 0x00000020, 110 },
  26         /* AXI */
  27         { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
  28         { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  29         { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  30                    DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  31         { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  32                    DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  33         { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  34                    DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  35         { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  36                    DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  37         { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  38         { DDRMC_CR126_PHY_RDLAT(11), 126 },
  39         { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
  40         { DDRMC_CR137_PHYCTL_DL(2), 137 },
  41         { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  42                    DDRMC_CR139_PHY_WRLV_DLL(3) |
  43                    DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  44         { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  45                    DDRMC_CR154_PAD_ZQ_MODE(1) |
  46                    DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  47                    DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
  48         { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
  49         { DDRMC_CR158_TWR(6), 158 },
  50         { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
  51                    DDRMC_CR161_TODTH_WR(6), 161 },
  52         /* end marker */
  53         { 0, -1 }
  54 };
  55
  56 /* PHY settings -- most of them differ from default in imx-regs.h */
  57
  58 #define PCM052_DDRMC_PHY_DQ_TIMING                      0x00002213
  59 #define PCM052_DDRMC_PHY_CTRL                           0x00290000
  60 #define PCM052_DDRMC_PHY_SLAVE_CTRL                     0x00002c00
  61 #define PCM052_DDRMC_PHY_PROC_PAD_ODT                   0x00010020
  62
  63 static struct ddrmc_phy_setting pcm052_phy_settings[] = {
  64         { PCM052_DDRMC_PHY_DQ_TIMING,  0 },
  65         { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
  66         { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
  67         { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
  68         { DDRMC_PHY_DQS_TIMING,  1 },
  69         { DDRMC_PHY_DQS_TIMING, 17 },
  70         { DDRMC_PHY_DQS_TIMING, 33 },
  71         { DDRMC_PHY_DQS_TIMING, 49 },
  72         { PCM052_DDRMC_PHY_CTRL,  2 },
  73         { PCM052_DDRMC_PHY_CTRL, 18 },
  74         { PCM052_DDRMC_PHY_CTRL, 34 },
  75         { DDRMC_PHY_MASTER_CTRL,  3 },
  76         { DDRMC_PHY_MASTER_CTRL, 19 },
  77         { DDRMC_PHY_MASTER_CTRL, 35 },
  78         { PCM052_DDRMC_PHY_SLAVE_CTRL,  4 },
  79         { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
  80         { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
  81         { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
  82         { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
  83
  84         /* end marker */
  85         { 0, -1 }
  86 };
  87
  88 int dram_init(void)
  89 {
  90 #if defined(CONFIG_TARGET_PCM052)
  91
  92         static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  93                 .tinit             = 5,
  94                 .trst_pwron        = 80000,
  95                 .cke_inactive      = 200000,
  96                 .wrlat             = 5,
  97                 .caslat_lin        = 12,
  98                 .trc               = 6,
  99                 .trrd              = 4,
 100                 .tccd              = 4,
 101                 .tbst_int_interval = 4,
 102                 .tfaw              = 18,
 103                 .trp               = 6,
 104                 .twtr              = 4,
 105                 .tras_min          = 15,
 106                 .tmrd              = 4,
 107                 .trtp              = 4,
 108                 .tras_max          = 14040,
 109                 .tmod              = 12,
 110                 .tckesr            = 4,
 111                 .tcke              = 3,
 112                 .trcd_int          = 6,
 113                 .tras_lockout      = 1,
 114                 .tdal              = 10,
 115                 .bstlen            = 3,
 116                 .tdll              = 512,
 117                 .trp_ab            = 6,
 118                 .tref              = 1542,
 119                 .trfc              = 64,
 120                 .tref_int          = 5,
 121                 .tpdex             = 3,
 122                 .txpdll            = 10,
 123                 .txsnr             = 68,
 124                 .txsr              = 506,
 125                 .cksrx             = 5,
 126                 .cksre             = 5,
 127                 .freq_chg_en       = 1,
 128                 .zqcl              = 256,
 129                 .zqinit            = 512,
 130                 .zqcs              = 64,
 131                 .ref_per_zq        = 64,
 132                 .zqcs_rotate       = 1,
 133                 .aprebit           = 10,
 134                 .cmd_age_cnt       = 255,
 135                 .age_cnt           = 255,
 136                 .q_fullness        = 0,
 137                 .odt_rd_mapcs0     = 1,
 138                 .odt_wr_mapcs0     = 1,
 139                 .wlmrd             = 40,
 140                 .wldqsen           = 25,
 141         };
 142
 143     const int row_diff = 2;
 144
 145 #elif defined(CONFIG_TARGET_BK4R1)
 146
 147         static const struct ddr3_jedec_timings pcm052_ddr_timings = {
 148                 .tinit             = 5,
 149                 .trst_pwron        = 80000,
 150                 .cke_inactive      = 200000,
 151                 .wrlat             = 5,
 152                 .caslat_lin        = 12,
 153                 .trc               = 6,
 154                 .trrd              = 4,
 155                 .tccd              = 4,
 156                 .tbst_int_interval = 0,
 157                 .tfaw              = 16,
 158                 .trp               = 6,
 159                 .twtr              = 4,
 160                 .tras_min          = 15,
 161                 .tmrd              = 4,
 162                 .trtp              = 4,
 163                 .tras_max          = 28080,
 164                 .tmod              = 12,
 165                 .tckesr            = 4,
 166                 .tcke              = 3,
 167                 .trcd_int          = 6,
 168                 .tras_lockout      = 1,
 169                 .tdal              = 12,
 170                 .bstlen            = 3,
 171                 .tdll              = 512,
 172                 .trp_ab            = 6,
 173                 .tref              = 3120,
 174                 .trfc              = 104,
 175                 .tref_int          = 0,
 176                 .tpdex             = 3,
 177                 .txpdll            = 10,
 178                 .txsnr             = 108,
 179                 .txsr              = 512,
 180                 .cksrx             = 5,
 181                 .cksre             = 5,
 182                 .freq_chg_en       = 1,
 183                 .zqcl              = 256,
 184                 .zqinit            = 512,
 185                 .zqcs              = 64,
 186                 .ref_per_zq        = 64,
 187                 .zqcs_rotate       = 1,
 188                 .aprebit           = 10,
 189                 .cmd_age_cnt       = 255,
 190                 .age_cnt           = 255,
 191                 .q_fullness        = 0,
 192                 .odt_rd_mapcs0     = 1,
 193                 .odt_wr_mapcs0     = 1,
 194                 .wlmrd             = 40,
 195                 .wldqsen           = 25,
 196         };
 197
 198     const int row_diff = 1;
 199
 200 #else /* Unknown PCM052 variant */
 201
 202 #error DDR characteristics undefined for this target. Please define them.
 203
 204 #endif
 205
 206         ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
 207                              pcm052_phy_settings, 1, row_diff);
 208
 209         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 210
 211         return 0;
 212 }
 213
 214 static void clock_init(void)
 215 {
 216         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 217         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 218
 219         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 220                         CCM_CCGR0_UART1_CTRL_MASK);
 221         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 222                         CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 223         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 224                         CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 225                         CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
 226                         CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
 227                         CCM_CCGR2_QSPI0_CTRL_MASK);
 228         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 229                         CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
 230         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 231                         CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 232                         CCM_CCGR4_GPC_CTRL_MASK);
 233         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 234                         CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 235         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 236                         CCM_CCGR7_SDHC1_CTRL_MASK);
 237         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 238                         CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 239         clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
 240                         CCM_CCGR10_NFC_CTRL_MASK);
 241
 242         clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 243                         ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
 244         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 245                         ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 246
 247         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 248                         CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
 249         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 250                         CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
 251                         CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
 252                         CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
 253                         CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
 254                         CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
 255                         CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
 256         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 257                         CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 258                         CCM_CACRR_ARM_CLK_DIV(0));
 259         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
 260                         CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
 261                         CCM_CSCMR1_QSPI0_CLK_SEL(3) |
 262                         CCM_CSCMR1_NFC_CLK_SEL(0));
 263         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 264                         CCM_CSCDR1_RMII_CLK_EN);
 265         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 266                         CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
 267                         CCM_CSCDR2_NFC_EN);
 268         clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
 269                         CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
 270                         CCM_CSCDR3_QSPI0_X2_DIV(1) |
 271                         CCM_CSCDR3_QSPI0_X4_DIV(3) |
 272                         CCM_CSCDR3_NFC_PRE_DIV(5));
 273         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 274                         CCM_CSCMR2_RMII_CLK_SEL(0));
 275 }
 276
 277 static void mscm_init(void)
 278 {
 279         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
 280         int i;
 281
 282         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
 283                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 284 }
 285
 286 int board_early_init_f(void)
 287 {
 288         clock_init();
 289         mscm_init();
 290
 291         return 0;
 292 }
 293
 294 int board_init(void)
 295 {
 296         struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
 297
 298         /* address of boot parameters */
 299         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 300
 301         /*
 302          * Enable external 32K Oscillator
 303          *
 304          * The internal clock experiences significant drift
 305          * so we must use the external oscillator in order
 306          * to maintain correct time in the hwclock
 307          */
 308         setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
 309
 310         return 0;
 311 }
 312
 313 #ifdef CONFIG_TARGET_BK4R1
 314 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 315 {
 316         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 317         struct fuse_bank *bank = &ocotp->bank[4];
 318         struct fuse_bank4_regs *fuse =
 319                 (struct fuse_bank4_regs *)bank->fuse_regs;
 320         u32 value;
 321
 322         /*
 323          * BK4 has different layout of stored MAC address
 324          * than one used in imx_get_mac_from_fuse() @ generic.c
 325          */
 326
 327         switch (dev_id) {
 328         case 0:
 329                 value = readl(&fuse->mac_addr1);
 330
 331                 mac[0] = value >> 8;
 332                 mac[1] = value;
 333
 334                 value = readl(&fuse->mac_addr0);
 335                 mac[2] = value >> 24;
 336                 mac[3] = value >> 16;
 337                 mac[4] = value >> 8;
 338                 mac[5] = value;
 339                 break;
 340         case 1:
 341                 value = readl(&fuse->mac_addr2);
 342
 343                 mac[0] = value >> 24;
 344                 mac[1] = value >> 16;
 345                 mac[2] = value >> 8;
 346                 mac[3] = value;
 347
 348                 value = readl(&fuse->mac_addr1);
 349                 mac[4] = value >> 24;
 350                 mac[5] = value >> 16;
 351                 break;
 352         }
 353 }
 354
 355 int board_late_init(void)
 356 {
 357         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 358         u32 reg;
 359
 360         if (IS_ENABLED(CONFIG_LED))
 361                 led_default_state();
 362
 363         /*
 364          * BK4r1 handle emergency/service SD card boot
 365          * Checking the SBMR1 register BOOTCFG1 byte:
 366          * NAND:
 367          *      bit [2] - NAND data width - 16
 368          *      bit [5] - NAND fast boot
 369          *      bit [7] = 1 - NAND as a source of booting
 370          * SD card (0x64):
 371          *      bit [4] = 0 - SD card source
 372          *      bit [6] = 1 - SD/MMC source
 373          */
 374
 375         reg = readl(&psrc->sbmr1);
 376         if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
 377             !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
 378                 printf("------ SD card boot -------\n");
 379                 set_default_env("!LVFBootloader", 0);
 380                 env_set("bootcmd",
 381                         "run prepare_install_bk4r1_envs; run install_bk4r1rs");
 382         }
 383
 384         return 0;
 385 }
 386
 387 /**
 388  * KSZ8081
 389  */
 390 #define MII_KSZ8081_REFERENCE_CLOCK_SELECT      0x1f
 391 #define RMII_50MHz_CLOCK        0x8180
 392
 393 int board_phy_config(struct phy_device *phydev)
 394 {
 395         /* Set 50 MHz reference clock */
 396         phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
 397                   RMII_50MHz_CLOCK);
 398
 399         return genphy_config(phydev);
 400 }
 401 #endif /* CONFIG_TARGET_BK4R1 */
 402
 403 int checkboard(void)
 404 {
 405 #ifdef CONFIG_TARGET_BK4R1
 406         puts("Board: BK4r1 (L333)\n");
 407 #else
 408         puts("Board: PCM-052\n");
 409 #endif
 410         return 0;
 411 }