board/liebherr/mccmon6/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Wandboard
   4  * Author: Tungyi Lin <tungyilin1127@gmail.com>
   5  *         Richard Hu <hakahu@gmail.com>
   6  */
   7
   8 #include <image.h>
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <errno.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc_imx.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <serial.h>
  24 #include <spl.h>
  25
  26 #include <asm/arch/mx6-ddr.h>
  27 /*
  28  * Driving strength:
  29  *   0x30 == 40 Ohm
  30  *   0x28 == 48 Ohm
  31  */
  32
  33 #define IMX6DQ_DRIVE_STRENGTH           0x30
  34 #define IMX6SDL_DRIVE_STRENGTH          0x28
  35
  36 /* configure MX6Q/DUAL mmdc DDR io registers */
  37 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  38         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  39         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  40         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  41         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  42         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  43         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  44         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  45         .dram_sdba2 = 0x00000000,
  46         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  47         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  48         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  49         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  50         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  51         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  52         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  53         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  54         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  55         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  56         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  57         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  58         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  59         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  60         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  61         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  62         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  63         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  64 };
  65
  66 /* configure MX6Q/DUAL mmdc GRP io registers */
  67 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  68         .grp_ddr_type = 0x000c0000,
  69         .grp_ddrmode_ctl = 0x00020000,
  70         .grp_ddrpke = 0x00000000,
  71         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  72         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  73         .grp_ddrmode = 0x00020000,
  74         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  75         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  76         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  77         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  78         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  79         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  80         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  81         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  82 };
  83
  84 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  85 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  86         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  87         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  88         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  89         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  90         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  91         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  92         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  93         .dram_sdba2 = 0x00000000,
  94         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  95         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  96         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  97         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  98         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  99         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 100         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 101         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 102         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 103         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 104         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 105         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 106         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 107         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 108         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 109         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 110         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 111         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 112 };
 113
 114 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 115 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 116         .grp_ddr_type = 0x000c0000,
 117         .grp_ddrmode_ctl = 0x00020000,
 118         .grp_ddrpke = 0x00000000,
 119         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 120         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 121         .grp_ddrmode = 0x00020000,
 122         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 123         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 124         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 125         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 126         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 127         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 128         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 129         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 130 };
 131
 132 /* H5T04G63AFR-PB */
 133 static struct mx6_ddr3_cfg h5t04g63afr = {
 134         .mem_speed = 1600,
 135         .density = 4,
 136         .width = 16,
 137         .banks = 8,
 138         .rowaddr = 15,
 139         .coladdr = 10,
 140         .pagesz = 2,
 141         .trcd = 1375,
 142         .trcmin = 4875,
 143         .trasmin = 3500,
 144 };
 145
 146 /* H5TQ2G63DFR-H9 */
 147 static struct mx6_ddr3_cfg h5tq2g63dfr = {
 148         .mem_speed = 1333,
 149         .density = 2,
 150         .width = 16,
 151         .banks = 8,
 152         .rowaddr = 14,
 153         .coladdr = 10,
 154         .pagesz = 2,
 155         .trcd = 1350,
 156         .trcmin = 4950,
 157         .trasmin = 3600,
 158 };
 159
 160 static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
 161         .p0_mpwldectrl0 = 0x001f001f,
 162         .p0_mpwldectrl1 = 0x001f001f,
 163         .p1_mpwldectrl0 = 0x001f001f,
 164         .p1_mpwldectrl1 = 0x001f001f,
 165         .p0_mpdgctrl0 = 0x4301030d,
 166         .p0_mpdgctrl1 = 0x03020277,
 167         .p1_mpdgctrl0 = 0x4300030a,
 168         .p1_mpdgctrl1 = 0x02780248,
 169         .p0_mprddlctl = 0x4536393b,
 170         .p1_mprddlctl = 0x36353441,
 171         .p0_mpwrdlctl = 0x41414743,
 172         .p1_mpwrdlctl = 0x462f453f,
 173 };
 174
 175 /* DDR 64bit 2GB */
 176 static struct mx6_ddr_sysinfo mem_q = {
 177         .dsize          = 2,
 178         .cs1_mirror     = 0,
 179         /* config for full 4GB range so that get_mem_size() works */
 180         .cs_density     = 32,
 181         .ncs            = 1,
 182         .bi_on          = 1,
 183         .rtt_nom        = 1,
 184         .rtt_wr         = 0,
 185         .ralat          = 5,
 186         .walat          = 0,
 187         .mif3_mode      = 3,
 188         .rst_to_cke     = 0x23,
 189         .sde_to_rst     = 0x10,
 190 };
 191
 192 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 193         .p0_mpwldectrl0 = 0x001f001f,
 194         .p0_mpwldectrl1 = 0x001f001f,
 195         .p1_mpwldectrl0 = 0x001f001f,
 196         .p1_mpwldectrl1 = 0x001f001f,
 197         .p0_mpdgctrl0 = 0x420e020e,
 198         .p0_mpdgctrl1 = 0x02000200,
 199         .p1_mpdgctrl0 = 0x42020202,
 200         .p1_mpdgctrl1 = 0x01720172,
 201         .p0_mprddlctl = 0x494c4f4c,
 202         .p1_mprddlctl = 0x4a4c4c49,
 203         .p0_mpwrdlctl = 0x3f3f3133,
 204         .p1_mpwrdlctl = 0x39373f2e,
 205 };
 206
 207 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
 208         .p0_mpwldectrl0 = 0x0040003c,
 209         .p0_mpwldectrl1 = 0x0032003e,
 210         .p0_mpdgctrl0 = 0x42350231,
 211         .p0_mpdgctrl1 = 0x021a0218,
 212         .p0_mprddlctl = 0x4b4b4e49,
 213         .p0_mpwrdlctl = 0x3f3f3035,
 214 };
 215
 216 /* DDR 64bit 1GB */
 217 static struct mx6_ddr_sysinfo mem_dl = {
 218         .dsize          = 2,
 219         .cs1_mirror     = 0,
 220         /* config for full 4GB range so that get_mem_size() works */
 221         .cs_density     = 32,
 222         .ncs            = 1,
 223         .bi_on          = 1,
 224         .rtt_nom        = 1,
 225         .rtt_wr         = 0,
 226         .ralat          = 5,
 227         .walat          = 0,
 228         .mif3_mode      = 3,
 229         .rst_to_cke     = 0x23,
 230         .sde_to_rst     = 0x10,
 231 };
 232
 233 /* DDR 32bit 512MB */
 234 static struct mx6_ddr_sysinfo mem_s = {
 235         .dsize          = 1,
 236         .cs1_mirror     = 0,
 237         /* config for full 4GB range so that get_mem_size() works */
 238         .cs_density     = 32,
 239         .ncs            = 1,
 240         .bi_on          = 1,
 241         .rtt_nom        = 1,
 242         .rtt_wr         = 0,
 243         .ralat          = 5,
 244         .walat          = 0,
 245         .mif3_mode      = 3,
 246         .rst_to_cke     = 0x23,
 247         .sde_to_rst     = 0x10,
 248 };
 249
 250 static void ccgr_init(void)
 251 {
 252         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 253
 254         writel(0x00C03F3F, &ccm->CCGR0);
 255         writel(0x0030FC03, &ccm->CCGR1);
 256         writel(0x0FFFC000, &ccm->CCGR2);
 257         writel(0x3FF00000, &ccm->CCGR3);
 258         writel(0x00FFF300, &ccm->CCGR4);
 259         writel(0x0F0000C3, &ccm->CCGR5);
 260         writel(0x000003FF, &ccm->CCGR6);
 261 }
 262
 263 static void spl_dram_init(void)
 264 {
 265         if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 266                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 267                 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
 268         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
 269                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 270                 mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
 271         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
 272                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 273                 mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
 274         }
 275
 276         udelay(100);
 277 }
 278
 279 static void setup_spi(void)
 280 {
 281         enable_spi_clk(true, 2);
 282 }
 283
 284 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
 285         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
 286         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 287
 288 static iomux_v3_cfg_t const uart1_pads[] = {
 289         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 290         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 291 };
 292
 293 static void setup_iomux_uart(void)
 294 {
 295         SETUP_IOMUX_PADS(uart1_pads);
 296 }
 297
 298 void board_init_f(ulong dummy)
 299 {
 300         ccgr_init();
 301
 302         /* setup AIPS and disable watchdog */
 303         arch_cpu_init();
 304
 305         gpr_init();
 306
 307         /* iomux */
 308         setup_iomux_uart();
 309
 310         /* setup GP timer */
 311         timer_init();
 312
 313         /* UART clocks enabled and gd valid - init serial console */
 314         preloader_console_init();
 315
 316         /* enable ECSPI clocks */
 317         setup_spi();
 318
 319         /* DDR initialization */
 320         spl_dram_init();
 321 }
 322
 323 void board_boot_order(u32 *spl_boot_list)
 324 {
 325         switch (spl_boot_device()) {
 326         case BOOT_DEVICE_MMC2:
 327         case BOOT_DEVICE_MMC1:
 328                 spl_boot_list[0] = BOOT_DEVICE_MMC2;
 329                 spl_boot_list[1] = BOOT_DEVICE_MMC1;
 330                 break;
 331
 332         case BOOT_DEVICE_NOR:
 333                 spl_boot_list[0] = BOOT_DEVICE_NOR;
 334                 break;
 335         }
 336 }
 337
 338 #ifdef CONFIG_SPL_LOAD_FIT
 339 int board_fit_config_name_match(const char *name)
 340 {
 341         return 0;
 342 }
 343 #endif
 344
 345 #ifdef CONFIG_SPL_OS_BOOT
 346 int spl_start_uboot(void)
 347 {
 348         char s[16];
 349         int ret;
 350         /*
 351          * We use BOOT_DEVICE_MMC1, but SD card is connected
 352          * to MMC2
 353          *
 354          * Correct "mapping" is delivered in board defined
 355          * board_boot_order() function.
 356          *
 357          * SD card boot is regarded as a "development" one,
 358          * hence we _always_ go through the u-boot.
 359          *
 360          */
 361         if (spl_boot_device() == BOOT_DEVICE_MMC1)
 362                 return 1;
 363
 364         /* break into full u-boot on 'c' */
 365         if (serial_tstc() && serial_getc() == 'c')
 366                 return 1;
 367
 368         env_init();
 369         ret = env_get_f("boot_os", s, sizeof(s));
 370         if ((ret != -1) && (strcmp(s, "no") == 0))
 371                 return 1;
 372
 373         /*
 374          * Check if SWUpdate recovery needs to be started
 375          *
 376          * recovery_status = NULL (not set - ret == -1) -> normal operation
 377          *
 378          * recovery_status = progress or
 379          * recovery_status = failed   or
 380          * recovery_status = <any value> -> start SWUpdate
 381          *
 382          */
 383         ret = env_get_f("recovery_status", s, sizeof(s));
 384         if (ret != -1)
 385                 return 1;
 386
 387         return 0;
 388 }
 389 #endif /* CONFIG_SPL_OS_BOOT */
 390
 391 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
 392         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
 393         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
 394
 395 #define NOR_WP                  IMX_GPIO_NR(1, 1)
 396
 397 static iomux_v3_cfg_t const eimnor_pads[] = {
 398         IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 399         IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 400         IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 401         IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 402         IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 403         IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 404         IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 405         IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 406         IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 407         IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 408         IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 409         IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 410         IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 411         IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 412         IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 413         IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 414         IOMUX_PADS(PAD_EIM_DA0__EIM_AD00   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 415         IOMUX_PADS(PAD_EIM_DA1__EIM_AD01   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 416         IOMUX_PADS(PAD_EIM_DA2__EIM_AD02   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 417         IOMUX_PADS(PAD_EIM_DA3__EIM_AD03   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 418         IOMUX_PADS(PAD_EIM_DA4__EIM_AD04   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 419         IOMUX_PADS(PAD_EIM_DA5__EIM_AD05   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 420         IOMUX_PADS(PAD_EIM_DA6__EIM_AD06   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 421         IOMUX_PADS(PAD_EIM_DA7__EIM_AD07   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 422         IOMUX_PADS(PAD_EIM_DA8__EIM_AD08   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 423         IOMUX_PADS(PAD_EIM_DA9__EIM_AD09   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 424         IOMUX_PADS(PAD_EIM_DA10__EIM_AD10  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 425         IOMUX_PADS(PAD_EIM_DA11__EIM_AD11  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 426         IOMUX_PADS(PAD_EIM_DA12__EIM_AD12  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 427         IOMUX_PADS(PAD_EIM_DA13__EIM_AD13  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 428         IOMUX_PADS(PAD_EIM_DA14__EIM_AD14  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 429         IOMUX_PADS(PAD_EIM_DA15__EIM_AD15  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 430         IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 431         IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 432         IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 433         IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 434         IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 435         IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 436         IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 437         IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 438         IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 439         IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 440         IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 441         IOMUX_PADS(PAD_EIM_RW__EIM_RW           | MUX_PAD_CTRL(NO_PAD_CTRL)),
 442         IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 443         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 444 };
 445
 446 static void eimnor_cs_setup(void)
 447 {
 448         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 449
 450         /* NOR configuration */
 451         writel(0x00620181, &weim_regs->cs0gcr1);
 452         writel(0x00000001, &weim_regs->cs0gcr2);
 453         writel(0x0b020000, &weim_regs->cs0rcr1);
 454         writel(0x0000b000, &weim_regs->cs0rcr2);
 455         writel(0x0804a240, &weim_regs->cs0wcr1);
 456         writel(0x00000000, &weim_regs->cs0wcr2);
 457
 458         writel(0x00000120, &weim_regs->wcr);
 459         writel(0x00000010, &weim_regs->wiar);
 460         writel(0x00000000, &weim_regs->ear);
 461
 462         set_chipselect_size(CS0_128);
 463 }
 464
 465 static void setup_eimnor(void)
 466 {
 467         SETUP_IOMUX_PADS(eimnor_pads);
 468         gpio_direction_output(NOR_WP, 1);
 469
 470         enable_eim_clk(1);
 471         eimnor_cs_setup();
 472 }
 473
 474 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
 475         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
 476         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 477
 478 #define USDHC2_CD_GPIO          IMX_GPIO_NR(1, 4)
 479
 480 static iomux_v3_cfg_t const usdhc2_pads[] = {
 481         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 482         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 483         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 484         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 485         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 486         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 487         /* Carrier MicroSD Card Detect */
 488         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 489 };
 490
 491 static iomux_v3_cfg_t const usdhc3_pads[] = {
 492         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 493         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 494         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 495         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 496         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 497         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 498         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 499         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 500         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 501         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 502         IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 503 };
 504
 505 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 506         {USDHC3_BASE_ADDR},
 507         {USDHC2_BASE_ADDR},
 508 };
 509
 510 int board_mmc_getcd(struct mmc *mmc)
 511 {
 512         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 513         int ret = 0;
 514
 515         switch (cfg->esdhc_base) {
 516         case USDHC2_BASE_ADDR:
 517                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 518                 break;
 519         case USDHC3_BASE_ADDR:
 520                 /*
 521                  * eMMC don't have card detect pin - since it is soldered to the
 522                  * PCB board
 523                  */
 524                 ret = 1;
 525                 break;
 526         }
 527         return ret;
 528 }
 529
 530 int board_mmc_init(bd_t *bis)
 531 {
 532         int ret;
 533         u32 index = 0;
 534
 535         /*
 536          * MMC MAP
 537          * (U-Boot device node)    (Physical Port)
 538          * mmc0                    Soldered on board eMMC device
 539          * mmc1                    MicroSD card
 540          */
 541         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 542                 switch (index) {
 543                 case 0:
 544                         SETUP_IOMUX_PADS(usdhc3_pads);
 545                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 546                         usdhc_cfg[0].max_bus_width = 8;
 547                         break;
 548                 case 1:
 549                         SETUP_IOMUX_PADS(usdhc2_pads);
 550                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 551                         usdhc_cfg[1].max_bus_width = 4;
 552                         gpio_direction_input(USDHC2_CD_GPIO);
 553                         break;
 554                 default:
 555                         printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
 556                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 557                         return -EINVAL;
 558                 }
 559
 560                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 561                 if (ret)
 562                         return ret;
 563         }
 564
 565         return 0;
 566 }
 567
 568 #ifdef CONFIG_SPL_BOARD_INIT
 569 #define DISPLAY_EN              IMX_GPIO_NR(1, 2)
 570 void spl_board_init(void)
 571 {
 572         setup_eimnor();
 573
 574         gpio_direction_output(DISPLAY_EN, 1);
 575 }
 576 #endif /* CONFIG_SPL_BOARD_INIT */