board/liebherr/display5/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <serial.h>
  14 #include <spl.h>
  15 #include <linux/libfdt.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/mx6-ddr.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include "asm/arch/crm_regs.h"
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include "asm/arch/iomux.h"
  24 #include <asm/mach-imx/iomux-v3.h>
  25 #include <asm/gpio.h>
  26 #include <fsl_esdhc_imx.h>
  27 #include <netdev.h>
  28 #include <bootcount.h>
  29 #include <watchdog.h>
  30 #include "common.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  35         .dram_sdclk_0 = 0x00000030,
  36         .dram_sdclk_1 = 0x00000030,
  37         .dram_cas = 0x00000030,
  38         .dram_ras = 0x00000030,
  39         .dram_reset = 0x00000030,
  40         .dram_sdcke0 = 0x00003000,
  41         .dram_sdcke1 = 0x00003000,
  42         .dram_sdba2 = 0x00000000,
  43         .dram_sdodt0 = 0x00000030,
  44         .dram_sdodt1 = 0x00000030,
  45
  46         .dram_sdqs0 = 0x00000030,
  47         .dram_sdqs1 = 0x00000030,
  48         .dram_sdqs2 = 0x00000030,
  49         .dram_sdqs3 = 0x00000030,
  50         .dram_sdqs4 = 0x00000030,
  51         .dram_sdqs5 = 0x00000030,
  52         .dram_sdqs6 = 0x00000030,
  53         .dram_sdqs7 = 0x00000030,
  54
  55         .dram_dqm0 = 0x00000030,
  56         .dram_dqm1 = 0x00000030,
  57         .dram_dqm2 = 0x00000030,
  58         .dram_dqm3 = 0x00000030,
  59         .dram_dqm4 = 0x00000030,
  60         .dram_dqm5 = 0x00000030,
  61         .dram_dqm6 = 0x00000030,
  62         .dram_dqm7 = 0x00000030,
  63 };
  64
  65 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  66         .grp_ddr_type = 0x000c0000,
  67         .grp_ddrmode_ctl = 0x00020000,
  68         .grp_ddrpke = 0x00000000,
  69         .grp_addds = 0x00000030,
  70         .grp_ctlds = 0x00000030,
  71         .grp_ddrmode = 0x00020000,
  72         .grp_b0ds = 0x00000030,
  73         .grp_b1ds = 0x00000030,
  74         .grp_b2ds = 0x00000030,
  75         .grp_b3ds = 0x00000030,
  76         .grp_b4ds = 0x00000030,
  77         .grp_b5ds = 0x00000030,
  78         .grp_b6ds = 0x00000030,
  79         .grp_b7ds = 0x00000030,
  80 };
  81
  82 /* 4x128Mx16.cfg */
  83 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  84         .p0_mpwldectrl0 = 0x002D0028,
  85         .p0_mpwldectrl1 = 0x0032002D,
  86         .p1_mpwldectrl0 = 0x00210036,
  87         .p1_mpwldectrl1 = 0x0019002E,
  88         .p0_mpdgctrl0 = 0x4349035C,
  89         .p0_mpdgctrl1 = 0x0348033D,
  90         .p1_mpdgctrl0 = 0x43550362,
  91         .p1_mpdgctrl1 = 0x03520316,
  92         .p0_mprddlctl = 0x41393940,
  93         .p1_mprddlctl = 0x3F3A3C47,
  94         .p0_mpwrdlctl = 0x413A423A,
  95         .p1_mpwrdlctl = 0x4042483E,
  96 };
  97
  98 /* MT41K128M16JT-125 (2Gb density) */
  99 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 100         .mem_speed = 1600,
 101         .density = 2,
 102         .width = 16,
 103         .banks = 8,
 104         .rowaddr = 14,
 105         .coladdr = 10,
 106         .pagesz = 2,
 107         .trcd = 1375,
 108         .trcmin = 4875,
 109         .trasmin = 3500,
 110 };
 111
 112 iomux_v3_cfg_t const uart_console_pads[] = {
 113         /* UART5 */
 114         MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 115         MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 116         MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 117         MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 118 };
 119
 120 void displ5_set_iomux_uart_spl(void)
 121 {
 122         SETUP_IOMUX_PADS(uart_console_pads);
 123 }
 124
 125 iomux_v3_cfg_t const misc_pads_spl[] = {
 126         /* Emergency recovery pin */
 127         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 128 };
 129
 130 void displ5_set_iomux_misc_spl(void)
 131 {
 132         SETUP_IOMUX_PADS(misc_pads_spl);
 133 }
 134
 135 #ifdef CONFIG_MXC_SPI
 136 iomux_v3_cfg_t const ecspi2_pads[] = {
 137         /* SPI2, NOR Flash nWP, CS0 */
 138         MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 139         MX6_PAD_CSI0_DAT9__ECSPI2_MOSI  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 140         MX6_PAD_CSI0_DAT8__ECSPI2_SCLK  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 141         MX6_PAD_CSI0_DAT11__GPIO5_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 142         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL),
 143 };
 144
 145 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 146 {
 147         if (bus != 1 || cs != 0)
 148                 return -EINVAL;
 149
 150         return IMX_GPIO_NR(5, 29);
 151 }
 152
 153 void displ5_set_iomux_ecspi_spl(void)
 154 {
 155         SETUP_IOMUX_PADS(ecspi2_pads);
 156 }
 157
 158 #else
 159 void displ5_set_iomux_ecspi_spl(void) {}
 160 #endif
 161
 162 #ifdef CONFIG_FSL_ESDHC_IMX
 163 iomux_v3_cfg_t const usdhc4_pads[] = {
 164         MX6_PAD_SD4_CLK__SD4_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD4_CMD__SD4_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD4_DAT0__SD4_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_SD4_DAT1__SD4_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_SD4_DAT2__SD4_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_SD4_DAT3__SD4_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170         MX6_PAD_SD4_DAT4__SD4_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         MX6_PAD_SD4_DAT5__SD4_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172         MX6_PAD_SD4_DAT6__SD4_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173         MX6_PAD_SD4_DAT7__SD4_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 174         MX6_PAD_NANDF_ALE__SD4_RESET    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175 };
 176
 177 void displ5_set_iomux_usdhc_spl(void)
 178 {
 179         SETUP_IOMUX_PADS(usdhc4_pads);
 180 }
 181
 182 #else
 183 void displ5_set_iomux_usdhc_spl(void) {}
 184 #endif
 185
 186 static void ccgr_init(void)
 187 {
 188         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 189
 190         writel(0x00C03F3F, &ccm->CCGR0);
 191         writel(0x0030FC3F, &ccm->CCGR1);
 192         writel(0x0FFFCFC0, &ccm->CCGR2);
 193         writel(0x3FF00000, &ccm->CCGR3);
 194         writel(0x00FFF300, &ccm->CCGR4);
 195         writel(0x0F0000C3, &ccm->CCGR5);
 196         writel(0x000003FF, &ccm->CCGR6);
 197 }
 198
 199 #ifdef CONFIG_MX6_DDRCAL
 200 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
 201 {
 202         struct mx6_mmdc_calibration calibration = {0};
 203
 204         mmdc_read_calibration(sysinfo, &calibration);
 205
 206         debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
 207         debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
 208         debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
 209         debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
 210         debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
 211         debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
 212         debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
 213         debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
 214         debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
 215         debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
 216         debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
 217         debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
 218 }
 219
 220 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
 221 {
 222         int ret;
 223
 224         /* Perform DDR DRAM calibration */
 225         udelay(100);
 226         ret = mmdc_do_write_level_calibration(sysinfo);
 227         if (ret) {
 228                 printf("DDR: Write level calibration error [%d]\n", ret);
 229                 return;
 230         }
 231
 232         ret = mmdc_do_dqs_calibration(sysinfo);
 233         if (ret) {
 234                 printf("DDR: DQS calibration error [%d]\n", ret);
 235                 return;
 236         }
 237
 238         spl_dram_print_cal(sysinfo);
 239 }
 240 #endif /* CONFIG_MX6_DDRCAL */
 241
 242 static void spl_dram_init(void)
 243 {
 244         struct mx6_ddr_sysinfo sysinfo = {
 245                 /* width of data bus:0=16,1=32,2=64 */
 246                 .dsize = 2,
 247                 /* config for full 4GB range so that get_mem_size() works */
 248                 .cs_density = 32, /* 32Gb per CS */
 249                 /* single chip select */
 250                 .ncs = 1,
 251                 .cs1_mirror = 0,
 252                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 253                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 254                 .walat = 1,     /* Write additional latency */
 255                 .ralat = 5,     /* Read additional latency */
 256                 .mif3_mode = 3, /* Command prediction working mode */
 257                 .bi_on = 1,     /* Bank interleaving enabled */
 258                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 259                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 260                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 261                 .ddr_type = DDR_TYPE_DDR3,
 262                 .refsel = 1,    /* Refresh cycles at 32KHz */
 263                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 264         };
 265
 266         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 267         mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
 268
 269 #ifdef CONFIG_MX6_DDRCAL
 270         spl_dram_perform_cal(&sysinfo);
 271 #endif
 272 }
 273
 274 #ifdef CONFIG_SPL_SPI_SUPPORT
 275 static void displ5_init_ecspi(void)
 276 {
 277         displ5_set_iomux_ecspi_spl();
 278         enable_spi_clk(1, 1);
 279 }
 280 #else
 281 static inline void displ5_init_ecspi(void) { }
 282 #endif
 283
 284 #ifdef CONFIG_SPL_MMC_SUPPORT
 285 static struct fsl_esdhc_cfg usdhc_cfg = {
 286         .esdhc_base = USDHC4_BASE_ADDR,
 287         .max_bus_width = 8,
 288 };
 289
 290 int board_mmc_init(bd_t *bd)
 291 {
 292         displ5_set_iomux_usdhc_spl();
 293
 294         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 295         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 296
 297         return fsl_esdhc_initialize(bd, &usdhc_cfg);
 298 }
 299 #endif
 300
 301 void board_init_f(ulong dummy)
 302 {
 303         ccgr_init();
 304
 305         arch_cpu_init();
 306
 307         gpr_init();
 308
 309         /* setup GP timer */
 310         timer_init();
 311
 312         displ5_set_iomux_uart_spl();
 313
 314         /* UART clocks enabled and gd valid - init serial console */
 315         preloader_console_init();
 316
 317         displ5_init_ecspi();
 318
 319         /* DDR initialization */
 320         spl_dram_init();
 321
 322         /* Clear the BSS. */
 323         memset(__bss_start, 0, __bss_end - __bss_start);
 324
 325         displ5_set_iomux_misc_spl();
 326
 327         /* Initialize and reset WDT in SPL */
 328         hw_watchdog_init();
 329         WATCHDOG_RESET();
 330
 331         /* load/boot image from boot device */
 332         board_init_r(NULL, 0);
 333 }
 334
 335 #define EM_PAD IMX_GPIO_NR(3, 29)
 336 int board_check_emergency_pad(void)
 337 {
 338         int ret;
 339
 340         ret = gpio_direction_input(EM_PAD);
 341         if (ret)
 342                 return ret;
 343
 344         return !gpio_get_value(EM_PAD);
 345 }
 346
 347 void board_boot_order(u32 *spl_boot_list)
 348 {
 349         /* Default boot sequence SPI -> MMC */
 350         spl_boot_list[0] = spl_boot_device();
 351         spl_boot_list[1] = BOOT_DEVICE_MMC1;
 352         spl_boot_list[2] = BOOT_DEVICE_UART;
 353         spl_boot_list[3] = BOOT_DEVICE_NONE;
 354
 355         /*
 356          * In case of emergency PAD pressed, we always boot
 357          * to proper u-boot and perform recovery tasks there.
 358          */
 359         if (board_check_emergency_pad())
 360                 return;
 361
 362 #ifdef CONFIG_SPL_ENV_SUPPORT
 363         /* 'fastboot' */
 364         const char *s;
 365
 366         if (env_init() || env_load())
 367                 return;
 368
 369         s = env_get("BOOT_FROM");
 370         if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
 371                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 372                 spl_boot_list[1] = spl_boot_device();
 373         }
 374 #endif
 375 }
 376
 377 void reset_cpu(ulong addr) {}
 378
 379 #ifdef CONFIG_SPL_LOAD_FIT
 380 int board_fit_config_name_match(const char *name)
 381 {
 382         return 0;
 383 }
 384 #endif
 385
 386 #ifdef CONFIG_SPL_OS_BOOT
 387 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
 388 int spl_start_uboot(void)
 389 {
 390         /* break into full u-boot on 'c' */
 391         if (serial_tstc() && serial_getc() == 'c')
 392                 return 1;
 393
 394 #ifdef CONFIG_SPL_ENV_SUPPORT
 395         if (env_get_yesno("boot_os") != 1)
 396                 return 1;
 397 #endif
 398         return 0;
 399 }
 400 #endif