board/liebherr/display5/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <serial.h>
  11 #include <spl.h>
  12 #include <linux/libfdt.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/mx6-ddr.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include "asm/arch/crm_regs.h"
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/imx-regs.h>
  20 #include "asm/arch/iomux.h"
  21 #include <asm/mach-imx/iomux-v3.h>
  22 #include <asm/gpio.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <netdev.h>
  25 #include <bootcount.h>
  26 #include <watchdog.h>
  27 #include "common.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  32         .dram_sdclk_0 = 0x00000030,
  33         .dram_sdclk_1 = 0x00000030,
  34         .dram_cas = 0x00000030,
  35         .dram_ras = 0x00000030,
  36         .dram_reset = 0x00000030,
  37         .dram_sdcke0 = 0x00003000,
  38         .dram_sdcke1 = 0x00003000,
  39         .dram_sdba2 = 0x00000000,
  40         .dram_sdodt0 = 0x00000030,
  41         .dram_sdodt1 = 0x00000030,
  42
  43         .dram_sdqs0 = 0x00000030,
  44         .dram_sdqs1 = 0x00000030,
  45         .dram_sdqs2 = 0x00000030,
  46         .dram_sdqs3 = 0x00000030,
  47         .dram_sdqs4 = 0x00000030,
  48         .dram_sdqs5 = 0x00000030,
  49         .dram_sdqs6 = 0x00000030,
  50         .dram_sdqs7 = 0x00000030,
  51
  52         .dram_dqm0 = 0x00000030,
  53         .dram_dqm1 = 0x00000030,
  54         .dram_dqm2 = 0x00000030,
  55         .dram_dqm3 = 0x00000030,
  56         .dram_dqm4 = 0x00000030,
  57         .dram_dqm5 = 0x00000030,
  58         .dram_dqm6 = 0x00000030,
  59         .dram_dqm7 = 0x00000030,
  60 };
  61
  62 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  63         .grp_ddr_type = 0x000c0000,
  64         .grp_ddrmode_ctl = 0x00020000,
  65         .grp_ddrpke = 0x00000000,
  66         .grp_addds = 0x00000030,
  67         .grp_ctlds = 0x00000030,
  68         .grp_ddrmode = 0x00020000,
  69         .grp_b0ds = 0x00000030,
  70         .grp_b1ds = 0x00000030,
  71         .grp_b2ds = 0x00000030,
  72         .grp_b3ds = 0x00000030,
  73         .grp_b4ds = 0x00000030,
  74         .grp_b5ds = 0x00000030,
  75         .grp_b6ds = 0x00000030,
  76         .grp_b7ds = 0x00000030,
  77 };
  78
  79 /* 4x128Mx16.cfg */
  80 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  81         .p0_mpwldectrl0 = 0x002D0028,
  82         .p0_mpwldectrl1 = 0x0032002D,
  83         .p1_mpwldectrl0 = 0x00210036,
  84         .p1_mpwldectrl1 = 0x0019002E,
  85         .p0_mpdgctrl0 = 0x4349035C,
  86         .p0_mpdgctrl1 = 0x0348033D,
  87         .p1_mpdgctrl0 = 0x43550362,
  88         .p1_mpdgctrl1 = 0x03520316,
  89         .p0_mprddlctl = 0x41393940,
  90         .p1_mprddlctl = 0x3F3A3C47,
  91         .p0_mpwrdlctl = 0x413A423A,
  92         .p1_mpwrdlctl = 0x4042483E,
  93 };
  94
  95 /* MT41K128M16JT-125 (2Gb density) */
  96 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  97         .mem_speed = 1600,
  98         .density = 2,
  99         .width = 16,
 100         .banks = 8,
 101         .rowaddr = 14,
 102         .coladdr = 10,
 103         .pagesz = 2,
 104         .trcd = 1375,
 105         .trcmin = 4875,
 106         .trasmin = 3500,
 107 };
 108
 109 iomux_v3_cfg_t const uart_console_pads[] = {
 110         /* UART5 */
 111         MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 112         MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 113         MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 114         MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 115 };
 116
 117 void displ5_set_iomux_uart_spl(void)
 118 {
 119         SETUP_IOMUX_PADS(uart_console_pads);
 120 }
 121
 122 iomux_v3_cfg_t const misc_pads_spl[] = {
 123         /* Emergency recovery pin */
 124         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 125 };
 126
 127 void displ5_set_iomux_misc_spl(void)
 128 {
 129         SETUP_IOMUX_PADS(misc_pads_spl);
 130 }
 131
 132 #ifdef CONFIG_MXC_SPI
 133 iomux_v3_cfg_t const ecspi2_pads[] = {
 134         /* SPI2, NOR Flash nWP, CS0 */
 135         MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 136         MX6_PAD_CSI0_DAT9__ECSPI2_MOSI  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 137         MX6_PAD_CSI0_DAT8__ECSPI2_SCLK  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 138         MX6_PAD_CSI0_DAT11__GPIO5_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 139         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL),
 140 };
 141
 142 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 143 {
 144         if (bus != 1 || cs != 0)
 145                 return -EINVAL;
 146
 147         return IMX_GPIO_NR(5, 29);
 148 }
 149
 150 void displ5_set_iomux_ecspi_spl(void)
 151 {
 152         SETUP_IOMUX_PADS(ecspi2_pads);
 153 }
 154
 155 #else
 156 void displ5_set_iomux_ecspi_spl(void) {}
 157 #endif
 158
 159 #ifdef CONFIG_FSL_ESDHC_IMX
 160 iomux_v3_cfg_t const usdhc4_pads[] = {
 161         MX6_PAD_SD4_CLK__SD4_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD4_CMD__SD4_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD4_DAT0__SD4_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD4_DAT1__SD4_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD4_DAT2__SD4_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD4_DAT3__SD4_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_SD4_DAT4__SD4_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_SD4_DAT5__SD4_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_SD4_DAT6__SD4_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170         MX6_PAD_SD4_DAT7__SD4_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         MX6_PAD_NANDF_ALE__SD4_RESET    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172 };
 173
 174 void displ5_set_iomux_usdhc_spl(void)
 175 {
 176         SETUP_IOMUX_PADS(usdhc4_pads);
 177 }
 178
 179 #else
 180 void displ5_set_iomux_usdhc_spl(void) {}
 181 #endif
 182
 183 static void ccgr_init(void)
 184 {
 185         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 186
 187         writel(0x00C03F3F, &ccm->CCGR0);
 188         writel(0x0030FC3F, &ccm->CCGR1);
 189         writel(0x0FFFCFC0, &ccm->CCGR2);
 190         writel(0x3FF00000, &ccm->CCGR3);
 191         writel(0x00FFF300, &ccm->CCGR4);
 192         writel(0x0F0000C3, &ccm->CCGR5);
 193         writel(0x000003FF, &ccm->CCGR6);
 194 }
 195
 196 #ifdef CONFIG_MX6_DDRCAL
 197 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
 198 {
 199         struct mx6_mmdc_calibration calibration = {0};
 200
 201         mmdc_read_calibration(sysinfo, &calibration);
 202
 203         debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
 204         debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
 205         debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
 206         debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
 207         debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
 208         debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
 209         debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
 210         debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
 211         debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
 212         debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
 213         debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
 214         debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
 215 }
 216
 217 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
 218 {
 219         int ret;
 220
 221         /* Perform DDR DRAM calibration */
 222         udelay(100);
 223         ret = mmdc_do_write_level_calibration(sysinfo);
 224         if (ret) {
 225                 printf("DDR: Write level calibration error [%d]\n", ret);
 226                 return;
 227         }
 228
 229         ret = mmdc_do_dqs_calibration(sysinfo);
 230         if (ret) {
 231                 printf("DDR: DQS calibration error [%d]\n", ret);
 232                 return;
 233         }
 234
 235         spl_dram_print_cal(sysinfo);
 236 }
 237 #endif /* CONFIG_MX6_DDRCAL */
 238
 239 static void spl_dram_init(void)
 240 {
 241         struct mx6_ddr_sysinfo sysinfo = {
 242                 /* width of data bus:0=16,1=32,2=64 */
 243                 .dsize = 2,
 244                 /* config for full 4GB range so that get_mem_size() works */
 245                 .cs_density = 32, /* 32Gb per CS */
 246                 /* single chip select */
 247                 .ncs = 1,
 248                 .cs1_mirror = 0,
 249                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 250                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 251                 .walat = 1,     /* Write additional latency */
 252                 .ralat = 5,     /* Read additional latency */
 253                 .mif3_mode = 3, /* Command prediction working mode */
 254                 .bi_on = 1,     /* Bank interleaving enabled */
 255                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 256                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 257                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 258                 .ddr_type = DDR_TYPE_DDR3,
 259                 .refsel = 1,    /* Refresh cycles at 32KHz */
 260                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 261         };
 262
 263         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 264         mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
 265
 266 #ifdef CONFIG_MX6_DDRCAL
 267         spl_dram_perform_cal(&sysinfo);
 268 #endif
 269 }
 270
 271 #ifdef CONFIG_SPL_SPI_SUPPORT
 272 static void displ5_init_ecspi(void)
 273 {
 274         displ5_set_iomux_ecspi_spl();
 275         enable_spi_clk(1, 1);
 276 }
 277 #else
 278 static inline void displ5_init_ecspi(void) { }
 279 #endif
 280
 281 #ifdef CONFIG_SPL_MMC_SUPPORT
 282 static struct fsl_esdhc_cfg usdhc_cfg = {
 283         .esdhc_base = USDHC4_BASE_ADDR,
 284         .max_bus_width = 8,
 285 };
 286
 287 int board_mmc_init(bd_t *bd)
 288 {
 289         displ5_set_iomux_usdhc_spl();
 290
 291         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 292         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 293
 294         return fsl_esdhc_initialize(bd, &usdhc_cfg);
 295 }
 296 #endif
 297
 298 void board_init_f(ulong dummy)
 299 {
 300         ccgr_init();
 301
 302         arch_cpu_init();
 303
 304         gpr_init();
 305
 306         /* setup GP timer */
 307         timer_init();
 308
 309         displ5_set_iomux_uart_spl();
 310
 311         /* UART clocks enabled and gd valid - init serial console */
 312         preloader_console_init();
 313
 314         displ5_init_ecspi();
 315
 316         /* DDR initialization */
 317         spl_dram_init();
 318
 319         /* Clear the BSS. */
 320         memset(__bss_start, 0, __bss_end - __bss_start);
 321
 322         displ5_set_iomux_misc_spl();
 323
 324         /* Initialize and reset WDT in SPL */
 325         hw_watchdog_init();
 326         WATCHDOG_RESET();
 327
 328         /* load/boot image from boot device */
 329         board_init_r(NULL, 0);
 330 }
 331
 332 #define EM_PAD IMX_GPIO_NR(3, 29)
 333 int board_check_emergency_pad(void)
 334 {
 335         int ret;
 336
 337         ret = gpio_direction_input(EM_PAD);
 338         if (ret)
 339                 return ret;
 340
 341         return !gpio_get_value(EM_PAD);
 342 }
 343
 344 void board_boot_order(u32 *spl_boot_list)
 345 {
 346         /* Default boot sequence SPI -> MMC */
 347         spl_boot_list[0] = spl_boot_device();
 348         spl_boot_list[1] = BOOT_DEVICE_MMC1;
 349         spl_boot_list[2] = BOOT_DEVICE_UART;
 350         spl_boot_list[3] = BOOT_DEVICE_NONE;
 351
 352         /*
 353          * In case of emergency PAD pressed, we always boot
 354          * to proper u-boot and perform recovery tasks there.
 355          */
 356         if (board_check_emergency_pad())
 357                 return;
 358
 359 #ifdef CONFIG_SPL_ENV_SUPPORT
 360         /* 'fastboot' */
 361         const char *s;
 362
 363         if (env_init() || env_load())
 364                 return;
 365
 366         s = env_get("BOOT_FROM");
 367         if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
 368                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 369                 spl_boot_list[1] = spl_boot_device();
 370         }
 371 #endif
 372 }
 373
 374 void reset_cpu(ulong addr) {}
 375
 376 #ifdef CONFIG_SPL_LOAD_FIT
 377 int board_fit_config_name_match(const char *name)
 378 {
 379         return 0;
 380 }
 381 #endif
 382
 383 #ifdef CONFIG_SPL_OS_BOOT
 384 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
 385 int spl_start_uboot(void)
 386 {
 387         /* break into full u-boot on 'c' */
 388         if (serial_tstc() && serial_getc() == 'c')
 389                 return 1;
 390
 391 #ifdef CONFIG_SPL_ENV_SUPPORT
 392         if (env_get_yesno("boot_os") != 1)
 393                 return 1;
 394 #endif
 395         return 0;
 396 }
 397 #endif