1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
9 #include <fdt_support.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/mx6-ddr.h>
18 #include <asm/arch/sys_proto.h>
23 #include <asm/mach-imx/iomux-v3.h>
24 #include <asm/mach-imx/boot_mode.h>
28 #include <linux/delay.h>
31 #include <dm/platform_data/serial_mxc.h>
32 #include <dm/platdata.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 static bool hw_ids_valid;
39 static bool sw_ids_valid;
43 const char *gpio_table_sw_names[] = {
44 "GPIO2_4", "GPIO2_5", "GPIO2_6", "GPIO2_7"
47 const char *gpio_table_sw_ids_names[] = {
48 "sw0", "sw1", "sw2", "sw3"
51 const char *gpio_table_hw_names[] = {
52 "GPIO6_7", "GPIO6_9", "GPIO6_10", "GPIO6_11",
53 "GPIO4_7", "GPIO4_11", "GPIO4_13", "GPIO4_15"
56 const char *gpio_table_hw_ids_names[] = {
57 "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
60 static int get_board_id(const char **pin_names, const char **ids_names,
61 int size, bool *valid, u32 *id)
63 struct gpio_desc desc;
68 for (i = 0; i < size; i++) {
69 memset(&desc, 0, sizeof(desc));
71 ret = dm_gpio_lookup_name(pin_names[i], &desc);
73 printf("Can't lookup request SWx gpios\n");
77 ret = dm_gpio_request(&desc, ids_names[i]);
79 printf("Can't lookup request SWx gpios\n");
83 dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
85 val = dm_gpio_get_value(&desc);
87 printf("Can't get SW%d ID\n", i);
100 gd->ram_size = imx_ddr_size();
105 iomux_v3_cfg_t const misc_pads[] = {
106 /* Prod ID GPIO pins */
107 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
108 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
109 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
110 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
112 /* HW revision GPIO pins */
113 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
114 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
115 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
116 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
117 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
118 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
119 MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
120 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
123 MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
125 /* Emergency recovery pin */
126 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
130 * Do not overwrite the console
131 * Always use serial for U-Boot console
133 int overwrite_console(void)
138 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
139 int ft_board_setup(void *blob, bd_t *bd)
141 fdt_fixup_ethernet(blob);
146 int board_phy_config(struct phy_device *phydev)
148 /* display5 due to PCB routing can only work with 100 Mbps */
149 phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
150 ADVERTISED_1000baseX_Full |
151 SUPPORTED_1000baseT_Half |
152 SUPPORTED_1000baseT_Full);
154 if (phydev->drv->config)
155 return phydev->drv->config(phydev);
162 struct gpio_desc phy_int_gbe, spi2_wp;
165 debug("board init\n");
166 /* address of boot parameters */
167 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
169 /* Setup misc (application specific) stuff */
170 SETUP_IOMUX_PADS(misc_pads);
172 get_board_id(gpio_table_sw_names, &gpio_table_sw_ids_names[0],
173 ARRAY_SIZE(gpio_table_sw_names), &sw_ids_valid, &unit_id);
174 debug("SWx unit_id 0x%x\n", unit_id);
176 get_board_id(gpio_table_hw_names, &gpio_table_hw_ids_names[0],
177 ARRAY_SIZE(gpio_table_hw_names), &hw_ids_valid, &cpu_id);
178 debug("HWx cpu_id 0x%x\n", cpu_id);
180 if (hw_ids_valid && sw_ids_valid)
181 printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
185 /* Setup low level FEC (ETH) */
186 ret = dm_gpio_lookup_name("GPIO1_28", &phy_int_gbe);
188 printf("Cannot get GPIO1_28\n");
190 ret = dm_gpio_request(&phy_int_gbe, "INT_GBE");
192 dm_gpio_set_dir_flags(&phy_int_gbe, GPIOD_IS_IN);
195 iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
196 enable_fec_anatop_clock(0, ENET_125MHZ);
198 /* Setup #WP for SPI-NOR memory */
199 ret = dm_gpio_lookup_name("GPIO7_0", &spi2_wp);
201 printf("Cannot get GPIO7_0\n");
203 ret = dm_gpio_request(&spi2_wp, "spi2_#wp");
205 dm_gpio_set_dir_flags(&spi2_wp, GPIOD_IS_OUT |
206 GPIOD_IS_OUT_ACTIVE);
212 #ifdef CONFIG_CMD_BMODE
213 static const struct boot_mode board_boot_modes[] = {
214 /* eMMC, USDHC-4, 8-bit bus width */
215 /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
216 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
217 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
221 static void setup_boot_modes(void)
223 add_board_boot_modes(board_boot_modes);
226 static inline void setup_boot_modes(void) {}
229 int misc_init_r(void)
231 struct gpio_desc em_pad;
236 ret = dm_gpio_lookup_name("GPIO3_29", &em_pad);
238 printf("Can't find emergency PAD gpio\n");
242 ret = dm_gpio_request(&em_pad, "Emergency_PAD");
244 printf("Can't request emergency PAD gpio\n");
248 dm_gpio_set_dir_flags(&em_pad, GPIOD_IS_IN);