1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
6 * Copyright 2011,2012 Freescale Semiconductor, Inc.
12 #include <linux/compiler.h>
14 #include <asm/processor.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_portals.h>
20 #include <asm/fsl_liodn.h>
23 #include "../common/common.h"
26 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
30 printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
35 /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
36 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
37 * For I2C only the low state is activly driven and high state is pulled-up
38 * by a resistor. Therefore the deblock GPIOs are used
39 * -> as an active output to drive a low state
40 * -> as an open-drain input to have a pulled-up high state
43 /* QRIO GPIOs used for deblocking */
44 #define DEBLOCK_PORT1 GPIO_A
45 #define DEBLOCK_SCL1 20
46 #define DEBLOCK_SDA1 21
48 /* By default deblock GPIOs are floating */
49 static void i2c_deblock_gpio_cfg(void)
51 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
52 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
53 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
55 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
56 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
59 void set_sda(int state)
61 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
64 void set_scl(int state)
66 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
71 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
76 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
82 #define RSTRQSR1_WDT_RR 0x00200000
83 #define RSTRQSR1_SW_RR 0x00100000
85 int board_early_init_f(void)
87 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
88 bool cpuwd_flag = false;
90 /* configure mode for uP reset request */
91 qrio_uprstreq(UPREQ_CORE_RST);
93 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
94 setbits_be32(&gur->ddrclkdr, 0x001f000f);
96 /* set reset reason according CPU register */
97 if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
101 qrio_cpuwd_flag(cpuwd_flag);
102 /* clear CPU bits by writing 1 */
103 setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
105 /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
106 qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
107 /* and enable WD on it */
108 qrio_wdmask(BFTIC4_RST, true);
110 /* set the ZL30138's prstcfg to reset at power-up only */
111 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
112 /* and take it out of reset as soon as possible (needed for Hooper) */
113 qrio_prst(ZL30158_RST, false, false);
118 int board_early_init_r(void)
121 /* Flush d-cache and invalidate i-cache of any FLASH data */
126 setup_qbman_portals();
128 ret = trigger_fpga_config();
130 printf("error triggering PCIe FPGA config\n");
132 /* enable the Unit LED (red) & Boot LED (on) */
135 /* enable Application Buffer */
136 qrio_enable_app_buffer();
141 unsigned long get_board_sys_clk(unsigned long dummy)
146 #define ETH_FRONT_PHY_RST 15
149 #define ZL30343_RST 9
151 int misc_init_f(void)
153 /* configure QRIO pis for i2c deblocking */
154 i2c_deblock_gpio_cfg();
156 /* configure the front phy's prstcfg and take it out of reset */
157 qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
158 qrio_prst(ETH_FRONT_PHY_RST, false, false);
160 /* set the ZL30343 prstcfg to reset at power-up only */
161 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
162 /* and enable the WD on it */
163 qrio_wdmask(ZL30343_RST, true);
165 /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
166 qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
167 qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
169 /* and enable the WD on them */
170 qrio_wdmask(QSFP1_RST, true);
171 qrio_wdmask(QSFP2_RST, true);
176 #define NUM_SRDS_BANKS 2
178 int misc_init_r(void)
180 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
181 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
182 SRDS_PLLCR0_RFCK_SEL_125};
185 /* check SERDES reference clocks */
186 for (i = 0; i < NUM_SRDS_BANKS; i++) {
187 u32 actual = in_be32(®s->bank[i].pllcr0);
188 actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
189 if (actual != expected[i]) {
190 printf("Warning: SERDES bank %u expects reference \
191 clock %sMHz, but actual is %sMHz\n", i + 1,
192 serdes_clock_to_string(expected[i]),
193 serdes_clock_to_string(actual));
197 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
201 #if defined(CONFIG_HUSH_INIT_VAR)
202 int hush_init_var(void)
204 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
209 #if defined(CONFIG_LAST_STAGE_INIT)
211 int last_stage_init(void)
213 #if defined(CONFIG_KMCOGE4)
214 /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
215 struct bfticu_iomap *bftic4 =
216 (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
217 u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
219 if (dip_switch != 0) {
220 /* start bootloader */
221 puts("DIP: Enabled\n");
222 env_set("actual_bank", "0");
231 #ifdef CONFIG_SYS_DPAA_FMAN
232 void fdt_fixup_fman_mac_addresses(void *blob)
236 unsigned char mac_addr[6];
238 /* get the mac addr from env */
239 tmp = env_get("ethaddr");
241 printf("ethaddr env variable not defined\n");
244 for (i = 0; i < 6; i++) {
245 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
247 tmp = (*end) ? end+1 : end;
250 /* find the correct fdt ethernet path and correct it */
251 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
253 printf("no /soc/fman/ethernet path offset\n");
256 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
258 printf("error setting local-mac-address property\n");
264 int ft_board_setup(void *blob, bd_t *bd)
269 ft_cpu_setup(blob, bd);
271 base = env_get_bootm_low();
272 size = env_get_bootm_size();
274 fdt_fixup_memory(blob, (u64)base, (u64)size);
276 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
277 fsl_fdt_fixup_dr_usb(blob, bd);
281 pci_of_setup(blob, bd);
284 fdt_fixup_liodn(blob);
285 #ifdef CONFIG_SYS_DPAA_FMAN
286 fdt_fixup_fman_ethernet(blob);
287 fdt_fixup_fman_mac_addresses(blob);
293 #if defined(CONFIG_POST)
295 /* DIC26_SELFTEST GPIO used to start factory test sw */
296 #define SELFTEST_PORT GPIO_A
297 #define SELFTEST_PIN 31
299 int post_hotkeys_pressed(void)
301 qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
302 return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);