1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * (C) Copyright 2008 - 2010
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
18 #include <fdt_support.h>
27 #include <asm/processor.h>
29 #include <linux/libfdt.h>
32 #include "../common/common.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
38 const qe_iop_conf_t qe_iop_conf_tab[] = {
39 /* port pin dir open_drain assign */
40 #if defined(CONFIG_ARCH_MPC8360)
42 {0, 1, 3, 0, 2}, /* MDIO */
43 {0, 2, 1, 0, 1}, /* MDC */
46 {1, 14, 1, 0, 1}, /* TxD0 */
47 {1, 15, 1, 0, 1}, /* TxD1 */
48 {1, 20, 2, 0, 1}, /* RxD0 */
49 {1, 21, 2, 0, 1}, /* RxD1 */
50 {1, 18, 1, 0, 1}, /* TX_EN */
51 {1, 26, 2, 0, 1}, /* RX_DV */
52 {1, 27, 2, 0, 1}, /* RX_ER */
53 {1, 24, 2, 0, 1}, /* COL */
54 {1, 25, 2, 0, 1}, /* CRS */
55 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
56 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
59 {5, 0, 1, 0, 2}, /* UART2_SOUT */
60 {5, 2, 1, 0, 1}, /* UART2_RTS */
61 {5, 3, 2, 0, 2}, /* UART2_SIN */
62 {5, 1, 2, 0, 3}, /* UART2_CTS */
63 #elif !defined(CONFIG_ARCH_MPC8309)
65 {0, 16, 1, 0, 3}, /* LA00 */
66 {0, 17, 1, 0, 3}, /* LA01 */
67 {0, 18, 1, 0, 3}, /* LA02 */
68 {0, 19, 1, 0, 3}, /* LA03 */
69 {0, 20, 1, 0, 3}, /* LA04 */
70 {0, 21, 1, 0, 3}, /* LA05 */
71 {0, 22, 1, 0, 3}, /* LA06 */
72 {0, 23, 1, 0, 3}, /* LA07 */
73 {0, 24, 1, 0, 3}, /* LA08 */
74 {0, 25, 1, 0, 3}, /* LA09 */
75 {0, 26, 1, 0, 3}, /* LA10 */
76 {0, 27, 1, 0, 3}, /* LA11 */
77 {0, 28, 1, 0, 3}, /* LA12 */
78 {0, 29, 1, 0, 3}, /* LA13 */
79 {0, 30, 1, 0, 3}, /* LA14 */
80 {0, 31, 1, 0, 3}, /* LA15 */
83 {3, 4, 3, 0, 2}, /* MDIO */
84 {3, 5, 1, 0, 2}, /* MDC */
87 {1, 18, 1, 0, 1}, /* TxD0 */
88 {1, 19, 1, 0, 1}, /* TxD1 */
89 {1, 22, 2, 0, 1}, /* RxD0 */
90 {1, 23, 2, 0, 1}, /* RxD1 */
91 {1, 26, 2, 0, 1}, /* RxER */
92 {1, 28, 2, 0, 1}, /* Rx_DV */
93 {1, 30, 1, 0, 1}, /* TxEN */
94 {1, 31, 2, 0, 1}, /* CRS */
95 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
99 {0, 0, 0, 0, QE_IOP_TAB_END},
102 #if defined(CONFIG_SUVD3)
103 const uint upma_table[] = {
104 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
105 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
106 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
107 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
108 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
109 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
110 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
111 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
112 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
113 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
114 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
115 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
116 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
117 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
118 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
119 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
123 static int piggy_present(void)
125 struct km_bec_fpga __iomem *base =
126 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
128 return in_8(&base->bprth) & PIGGY_PRESENT;
131 int ethernet_present(void)
133 return piggy_present();
136 int board_early_init_r(void)
138 struct km_bec_fpga *base =
139 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
140 #if defined(CONFIG_SUVD3)
141 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
142 fsl_lbc_t *lbc = &immap->im_lbc;
143 u32 *mxmr = &lbc->mamr;
146 #if defined(CONFIG_ARCH_MPC8360)
149 * Because of errata in the UCCs, we have to write to the reserved
150 * registers to slow the clocks down.
152 svid = SVR_REV(mfspr(SVR));
156 * MPC8360ECE.pdf QE_ENET10 table 4:
157 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
158 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
160 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
164 * MPC8360ECE.pdf QE_ENET10 table 4:
165 * IMMR + 0x14AC[24:27] = 1010
167 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
168 0x00000050, 0x000000a0);
173 /* enable the PHY on the PIGGY */
174 setbits_8(&base->pgy_eth, 0x01);
175 /* enable the Unit LED (green) */
176 setbits_8(&base->oprth, WRL_BOOT);
177 /* enable Application Buffer */
178 setbits_8(&base->oprtl, OPRTL_XBUFENA);
180 #if defined(CONFIG_SUVD3)
181 /* configure UPMA for APP1 */
182 upmconfig(UPMA, (uint *) upma_table,
183 sizeof(upma_table) / sizeof(uint));
184 out_be32(mxmr, CONFIG_SYS_MAMR);
189 int misc_init_r(void)
191 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
192 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
196 int last_stage_init(void)
198 #if defined(CONFIG_TARGET_KMCOGE5NE)
199 struct bfticu_iomap *base =
200 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
201 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
203 if (dip_switch != 0) {
204 /* start bootloader */
205 puts("DIP: Enabled\n");
206 env_set("actual_bank", "0");
213 static int fixed_sdram(void)
215 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
220 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
221 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
222 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
223 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
224 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
225 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
226 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
227 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
228 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
229 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
230 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
231 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
232 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
234 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
236 msize = CONFIG_SYS_DDR_SIZE << 20;
237 disable_addr_trans();
238 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
240 msize /= (1024 * 1024);
241 if (CONFIG_SYS_DDR_SIZE != msize) {
242 for (ddr_size = msize << 20, ddr_size_log2 = 0;
244 ddr_size = ddr_size >> 1, ddr_size_log2++)
247 out_be32(&im->sysconf.ddrlaw[0].ar,
248 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
249 out_be32(&im->ddr.csbnds[0].csbnds,
250 (((msize / 16) - 1) & 0xff));
258 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
261 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
264 out_be32(&im->sysconf.ddrlaw[0].bar,
265 CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
266 msize = fixed_sdram();
268 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
270 * Initialize DDR ECC byte
272 ddr_enable_ecc(msize * 1024 * 1024);
275 /* return total bus SDRAM size(bytes) -- DDR */
276 gd->ram_size = msize * 1024 * 1024;
283 puts("Board: ABB " CONFIG_SYS_CONFIG_NAME);
286 puts(" with PIGGY.");
291 int ft_board_setup(void *blob, bd_t *bd)
293 ft_cpu_setup(blob, bd);
298 #if defined(CONFIG_HUSH_INIT_VAR)
299 int hush_init_var(void)
301 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
306 #if defined(CONFIG_POST)
307 int post_hotkeys_pressed(void)
310 struct km_bec_fpga *base =
311 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
312 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
313 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
314 debug("post_hotkeys_pressed: %d\n", !testpin);
318 ulong post_word_load(void)
320 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
321 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
322 return in_le32(addr);
325 void post_word_store(ulong value)
327 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
328 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
329 out_le32(addr, value);
332 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
335 * These match CONFIG_SYS_MEMTEST_START and
336 * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START)
338 *vstart = 0x00100000;
340 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);