board/isee/igep003x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
   4  *
   5  * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
   6  */
   7
   8 #include <common.h>
   9 #include <env.h>
  10 #include <errno.h>
  11 #include <init.h>
  12 #include <serial.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/io.h>
  23 #include <asm/emif.h>
  24 #include <asm/gpio.h>
  25 #include <i2c.h>
  26 #include <miiphy.h>
  27 #include <cpsw.h>
  28 #include <fdt_support.h>
  29 #include <mtd_node.h>
  30 #include <jffs2/load_kernel.h>
  31 #include "board.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  36  * and control IGEP0034 green and red LEDs.
  37  * U-boot configures these pins as input pullup to detect board revision:
  38  * IGEP0034-LITE = 0b00
  39  * IGEP0034 (FULL) = 0b01
  40  * IGEP0033 = 0b1X
  41  */
  42 #define GPIO_GREEN_REVISION     27
  43 #define GPIO_RED_REVISION       26
  44
  45 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  46
  47 /*
  48  * Routine: get_board_revision
  49  * Description: Returns the board revision
  50  */
  51 static int get_board_revision(void)
  52 {
  53         int revision;
  54
  55         gpio_request(GPIO_GREEN_REVISION, "green_revision");
  56         gpio_direction_input(GPIO_GREEN_REVISION);
  57         revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
  58         gpio_free(GPIO_GREEN_REVISION);
  59
  60         gpio_request(GPIO_RED_REVISION, "red_revision");
  61         gpio_direction_input(GPIO_RED_REVISION);
  62         revision = revision + gpio_get_value(GPIO_RED_REVISION);
  63         gpio_free(GPIO_RED_REVISION);
  64
  65         return revision;
  66 }
  67
  68 #ifdef CONFIG_SPL_BUILD
  69 /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
  70 static const struct ddr_data ddr3_igep0034_data = {
  71         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  72         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  73         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  74         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  75 };
  76
  77 static const struct ddr_data ddr3_igep0034_lite_data = {
  78         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  79         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  80         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  81         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  82 };
  83
  84 static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
  85         .cmd0csratio = MT41K256M16HA125E_RATIO,
  86         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  87
  88         .cmd1csratio = MT41K256M16HA125E_RATIO,
  89         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  90
  91         .cmd2csratio = MT41K256M16HA125E_RATIO,
  92         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  93 };
  94
  95 static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
  96         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  97         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  98
  99         .cmd1csratio = K4B2G1646EBIH9_RATIO,
 100         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 101
 102         .cmd2csratio = K4B2G1646EBIH9_RATIO,
 103         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 104 };
 105
 106 static struct emif_regs ddr3_igep0034_emif_reg_data = {
 107         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 108         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 109         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 110         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 111         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 112         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 113         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 114 };
 115
 116 static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
 117         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
 118         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
 119         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
 120         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
 121         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
 122         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
 123         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
 124 };
 125
 126 const struct ctrl_ioregs ioregs_igep0034 = {
 127         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 128         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 129         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 130         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 131         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 132 };
 133
 134 const struct ctrl_ioregs ioregs_igep0034_lite = {
 135         .cm0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 136         .cm1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 137         .cm2ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 138         .dt0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 139         .dt1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 140 };
 141
 142 #define OSC    (V_OSCK/1000000)
 143 const struct dpll_params dpll_ddr = {
 144                 400, OSC-1, 1, -1, -1, -1, -1};
 145
 146 const struct dpll_params *get_dpll_ddr_params(void)
 147 {
 148         return &dpll_ddr;
 149 }
 150
 151 void set_uart_mux_conf(void)
 152 {
 153         enable_uart0_pin_mux();
 154 }
 155
 156 void set_mux_conf_regs(void)
 157 {
 158         enable_board_pin_mux();
 159 }
 160
 161 void sdram_init(void)
 162 {
 163         if (get_board_revision() == 1)
 164                 config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
 165                         &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
 166         else
 167                 config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
 168                         &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
 169 }
 170
 171 #ifdef CONFIG_SPL_OS_BOOT
 172 int spl_start_uboot(void)
 173 {
 174         /* break into full u-boot on 'c' */
 175         return serial_tstc() && serial_getc() == 'c';
 176 }
 177 #endif
 178 #endif
 179
 180 /*
 181  * Basic board specific setup.  Pinmux has been handled already.
 182  */
 183 int board_init(void)
 184 {
 185         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 186
 187         gpmc_init();
 188
 189         return 0;
 190 }
 191
 192 #ifdef CONFIG_BOARD_LATE_INIT
 193 int board_late_init(void)
 194 {
 195 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 196         switch (get_board_revision()) {
 197                 case 0:
 198                         env_set("board_name", "igep0034-lite");
 199                         break;
 200                 case 1:
 201                         env_set("board_name", "igep0034");
 202                         break;
 203                 default:
 204                         env_set("board_name", "igep0033");
 205                         break;
 206         }
 207 #endif
 208         return 0;
 209 }
 210 #endif
 211
 212 #ifdef CONFIG_OF_BOARD_SETUP
 213 int ft_board_setup(void *blob, bd_t *bd)
 214 {
 215 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 216         static const struct node_info nodes[] = {
 217                 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
 218         };
 219
 220         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 221 #endif
 222         return 0;
 223 }
 224 #endif
 225
 226 #if defined(CONFIG_DRIVER_TI_CPSW)
 227 static void cpsw_control(int enabled)
 228 {
 229         /* VTP can be added here */
 230
 231         return;
 232 }
 233
 234 static struct cpsw_slave_data cpsw_slaves[] = {
 235         {
 236                 .slave_reg_ofs  = 0x208,
 237                 .sliver_reg_ofs = 0xd80,
 238                 .phy_addr       = 0,
 239                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 240         },
 241 };
 242
 243 static struct cpsw_platform_data cpsw_data = {
 244         .mdio_base              = CPSW_MDIO_BASE,
 245         .cpsw_base              = CPSW_BASE,
 246         .mdio_div               = 0xff,
 247         .channels               = 8,
 248         .cpdma_reg_ofs          = 0x800,
 249         .slaves                 = 1,
 250         .slave_data             = cpsw_slaves,
 251         .ale_reg_ofs            = 0xd00,
 252         .ale_entries            = 1024,
 253         .host_port_reg_ofs      = 0x108,
 254         .hw_stats_reg_ofs       = 0x900,
 255         .bd_ram_ofs             = 0x2000,
 256         .mac_control            = (1 << 5),
 257         .control                = cpsw_control,
 258         .host_port_num          = 0,
 259         .version                = CPSW_CTRL_VERSION_2,
 260 };
 261
 262 int board_eth_init(bd_t *bis)
 263 {
 264         int rv, ret = 0;
 265         uint8_t mac_addr[6];
 266         uint32_t mac_hi, mac_lo;
 267
 268         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 269                 /* try reading mac address from efuse */
 270                 mac_lo = readl(&cdev->macid0l);
 271                 mac_hi = readl(&cdev->macid0h);
 272                 mac_addr[0] = mac_hi & 0xFF;
 273                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 274                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 275                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 276                 mac_addr[4] = mac_lo & 0xFF;
 277                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 278                 if (is_valid_ethaddr(mac_addr))
 279                         eth_env_set_enetaddr("ethaddr", mac_addr);
 280         }
 281
 282         writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
 283                &cdev->miisel);
 284
 285         if (get_board_revision() == 1)
 286                 cpsw_slaves[0].phy_addr = 1;
 287
 288         rv = cpsw_register(&cpsw_data);
 289         if (rv < 0)
 290                 printf("Error %d registering CPSW switch\n", rv);
 291         else
 292                 ret += rv;
 293
 294         return ret;
 295 }
 296 #endif