board/isee/igep003x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
   4  *
   5  * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
   6  */
   7
   8 #include <common.h>
   9 #include <env.h>
  10 #include <errno.h>
  11 #include <init.h>
  12 #include <malloc.h>
  13 #include <serial.h>
  14 #include <spl.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/omap.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/mmc_host_def.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <i2c.h>
  27 #include <miiphy.h>
  28 #include <cpsw.h>
  29 #include <fdt_support.h>
  30 #include <mtd_node.h>
  31 #include <jffs2/load_kernel.h>
  32 #include "board.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  37  * and control IGEP0034 green and red LEDs.
  38  * U-boot configures these pins as input pullup to detect board revision:
  39  * IGEP0034-LITE = 0b00
  40  * IGEP0034 (FULL) = 0b01
  41  * IGEP0033 = 0b1X
  42  */
  43 #define GPIO_GREEN_REVISION     27
  44 #define GPIO_RED_REVISION       26
  45
  46 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  47
  48 /*
  49  * Routine: get_board_revision
  50  * Description: Returns the board revision
  51  */
  52 static int get_board_revision(void)
  53 {
  54         int revision;
  55
  56         gpio_request(GPIO_GREEN_REVISION, "green_revision");
  57         gpio_direction_input(GPIO_GREEN_REVISION);
  58         revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
  59         gpio_free(GPIO_GREEN_REVISION);
  60
  61         gpio_request(GPIO_RED_REVISION, "red_revision");
  62         gpio_direction_input(GPIO_RED_REVISION);
  63         revision = revision + gpio_get_value(GPIO_RED_REVISION);
  64         gpio_free(GPIO_RED_REVISION);
  65
  66         return revision;
  67 }
  68
  69 #ifdef CONFIG_SPL_BUILD
  70 /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
  71 static const struct ddr_data ddr3_igep0034_data = {
  72         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  73         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  74         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  75         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  76 };
  77
  78 static const struct ddr_data ddr3_igep0034_lite_data = {
  79         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  80         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  81         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  82         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  83 };
  84
  85 static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
  86         .cmd0csratio = MT41K256M16HA125E_RATIO,
  87         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  88
  89         .cmd1csratio = MT41K256M16HA125E_RATIO,
  90         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  91
  92         .cmd2csratio = MT41K256M16HA125E_RATIO,
  93         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  94 };
  95
  96 static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
  97         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  98         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  99
 100         .cmd1csratio = K4B2G1646EBIH9_RATIO,
 101         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 102
 103         .cmd2csratio = K4B2G1646EBIH9_RATIO,
 104         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 105 };
 106
 107 static struct emif_regs ddr3_igep0034_emif_reg_data = {
 108         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 109         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 110         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 111         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 112         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 113         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 114         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 115 };
 116
 117 static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
 118         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
 119         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
 120         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
 121         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
 122         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
 123         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
 124         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
 125 };
 126
 127 const struct ctrl_ioregs ioregs_igep0034 = {
 128         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 129         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 130         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 131         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 132         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 133 };
 134
 135 const struct ctrl_ioregs ioregs_igep0034_lite = {
 136         .cm0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 137         .cm1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 138         .cm2ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 139         .dt0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 140         .dt1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 141 };
 142
 143 #define OSC    (V_OSCK/1000000)
 144 const struct dpll_params dpll_ddr = {
 145                 400, OSC-1, 1, -1, -1, -1, -1};
 146
 147 const struct dpll_params *get_dpll_ddr_params(void)
 148 {
 149         return &dpll_ddr;
 150 }
 151
 152 void set_uart_mux_conf(void)
 153 {
 154         enable_uart0_pin_mux();
 155 }
 156
 157 void set_mux_conf_regs(void)
 158 {
 159         enable_board_pin_mux();
 160 }
 161
 162 void sdram_init(void)
 163 {
 164         if (get_board_revision() == 1)
 165                 config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
 166                         &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
 167         else
 168                 config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
 169                         &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
 170 }
 171
 172 #ifdef CONFIG_SPL_OS_BOOT
 173 int spl_start_uboot(void)
 174 {
 175         /* break into full u-boot on 'c' */
 176         return serial_tstc() && serial_getc() == 'c';
 177 }
 178 #endif
 179 #endif
 180
 181 /*
 182  * Basic board specific setup.  Pinmux has been handled already.
 183  */
 184 int board_init(void)
 185 {
 186         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 187
 188         gpmc_init();
 189
 190         return 0;
 191 }
 192
 193 #ifdef CONFIG_BOARD_LATE_INIT
 194 int board_late_init(void)
 195 {
 196 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 197         switch (get_board_revision()) {
 198                 case 0:
 199                         env_set("board_name", "igep0034-lite");
 200                         break;
 201                 case 1:
 202                         env_set("board_name", "igep0034");
 203                         break;
 204                 default:
 205                         env_set("board_name", "igep0033");
 206                         break;
 207         }
 208 #endif
 209         return 0;
 210 }
 211 #endif
 212
 213 #ifdef CONFIG_OF_BOARD_SETUP
 214 int ft_board_setup(void *blob, bd_t *bd)
 215 {
 216 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 217         static const struct node_info nodes[] = {
 218                 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
 219         };
 220
 221         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 222 #endif
 223         return 0;
 224 }
 225 #endif
 226
 227 #if defined(CONFIG_DRIVER_TI_CPSW)
 228 static void cpsw_control(int enabled)
 229 {
 230         /* VTP can be added here */
 231
 232         return;
 233 }
 234
 235 static struct cpsw_slave_data cpsw_slaves[] = {
 236         {
 237                 .slave_reg_ofs  = 0x208,
 238                 .sliver_reg_ofs = 0xd80,
 239                 .phy_addr       = 0,
 240                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 241         },
 242 };
 243
 244 static struct cpsw_platform_data cpsw_data = {
 245         .mdio_base              = CPSW_MDIO_BASE,
 246         .cpsw_base              = CPSW_BASE,
 247         .mdio_div               = 0xff,
 248         .channels               = 8,
 249         .cpdma_reg_ofs          = 0x800,
 250         .slaves                 = 1,
 251         .slave_data             = cpsw_slaves,
 252         .ale_reg_ofs            = 0xd00,
 253         .ale_entries            = 1024,
 254         .host_port_reg_ofs      = 0x108,
 255         .hw_stats_reg_ofs       = 0x900,
 256         .bd_ram_ofs             = 0x2000,
 257         .mac_control            = (1 << 5),
 258         .control                = cpsw_control,
 259         .host_port_num          = 0,
 260         .version                = CPSW_CTRL_VERSION_2,
 261 };
 262
 263 int board_eth_init(bd_t *bis)
 264 {
 265         int rv, ret = 0;
 266         uint8_t mac_addr[6];
 267         uint32_t mac_hi, mac_lo;
 268
 269         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 270                 /* try reading mac address from efuse */
 271                 mac_lo = readl(&cdev->macid0l);
 272                 mac_hi = readl(&cdev->macid0h);
 273                 mac_addr[0] = mac_hi & 0xFF;
 274                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 275                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 276                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 277                 mac_addr[4] = mac_lo & 0xFF;
 278                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 279                 if (is_valid_ethaddr(mac_addr))
 280                         eth_env_set_enetaddr("ethaddr", mac_addr);
 281         }
 282
 283         writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
 284                &cdev->miisel);
 285
 286         if (get_board_revision() == 1)
 287                 cpsw_slaves[0].phy_addr = 1;
 288
 289         rv = cpsw_register(&cpsw_data);
 290         if (rv < 0)
 291                 printf("Error %d registering CPSW switch\n", rv);
 292         else
 293                 ret += rv;
 294
 295         return ret;
 296 }
 297 #endif