1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
11 #include <asm/cache.h>
13 #include <dm/platform_data/serial_pl01x.h>
14 #include <asm/arch/hi3798cv200.h>
15 #include <asm/armv8/mmu.h>
16 #include <linux/delay.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 static struct mm_region poplar_mem_map[] = {
25 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
31 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
33 PTE_BLOCK_PXN | PTE_BLOCK_UXN
39 struct mm_region *mem_map = poplar_mem_map;
41 #if !CONFIG_IS_ENABLED(OF_CONTROL)
42 static const struct pl01x_serial_platdata serial_platdata = {
43 .base = REG_BASE_UART0,
48 U_BOOT_DEVICE(poplar_serial) = {
49 .name = "serial_pl01x",
50 .platdata = &serial_platdata,
56 puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
61 void reset_cpu(ulong addr)
68 gd->ram_size = get_ram_size(NULL, 0x80000000);
74 * Some linux kernel versions don't use memory before its load address, so to
75 * be generic we just pretend it isn't there. In previous uboot versions we
76 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
77 * could persist in memory and be left alone by the kernel.
79 * That led to a problem when mapping memory in older kernels. That PSCI code
80 * now lies in memory below the kernel load offset; it therefore won't be
81 * touched by the kernel, and by not specially reserving it we avoid the mapping
85 #define KERNEL_TEXT_OFFSET 0x00080000
87 int dram_init_banksize(void)
89 gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
90 gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
95 static void usb2_phy_config(void)
97 const u32 config[] = {
98 /* close EOP pre-emphasis. open data pre-emphasis */
100 /* Rcomp = 150mW, increase DC level */
102 /* keep Rcomp working */
104 /* Icomp = 212mW, increase current drive */
106 /* EMI fix: rx_active not stay 1 when error packets received */
108 /* Comp mode select */
110 /* adjust eye diagram */
112 /* adjust eye diagram */
117 for (i = 0; i < ARRAY_SIZE(config); i++) {
118 writel(config[i], PERI_CTRL_USB0);
119 clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
124 static void usb2_phy_init(void)
126 /* reset usb2 controller bus/utmi/roothub */
127 setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
128 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
131 /* reset usb2 phy por/utmi */
132 setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
135 /* open usb2 ref clk */
136 setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
139 /* cancel usb2 power on reset */
140 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
145 /* cancel usb2 port reset, wait comp circuit stable */
146 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
149 /* open usb2 controller clk */
150 setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
151 USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
152 USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
155 /* cancel usb2 control reset */
156 clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
157 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
161 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
164 #include <usb/dwc2_udc.h>
167 static struct dwc2_plat_otg_data poplar_otg_data = {
168 .regs_otg = HIOTG_BASE_ADDR
171 static void set_usb_to_device(void)
173 setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
176 int board_usb_init(int index, enum usb_init_type init)
179 return dwc2_udc_probe(&poplar_otg_data);
182 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
184 if (!env_get("serial#"))
185 g_dnl_set_serialnumber("0123456789POPLAR");