1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Linaro
4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 #include <asm/arch/hi3660.h>
12 #include <asm/armv8/mmu.h>
14 #include <linux/arm-smccc.h>
15 #include <linux/psci.h>
17 #define PMIC_REG_TO_BUS_ADDR(x) (x << 2)
18 #define PMIC_VSEL_MASK 0x7
20 DECLARE_GLOBAL_DATA_PTR;
22 #if !CONFIG_IS_ENABLED(OF_CONTROL)
23 #include <dm/platform_data/serial_pl01x.h>
25 static const struct pl01x_serial_platdata serial_platdata = {
26 .base = HI3660_UART6_BASE,
31 U_BOOT_DEVICE(hikey960_serial0) = {
32 .name = "serial_pl01x",
33 .platdata = &serial_platdata,
37 static struct mm_region hikey_mem_map[] = {
39 .virt = 0x0UL, /* DDR */
42 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45 .virt = 0xE0000000UL, /* Peripheral block */
48 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
50 PTE_BLOCK_PXN | PTE_BLOCK_UXN
57 struct mm_region *mem_map = hikey_mem_map;
59 int board_early_init_f(void)
71 gd->ram_size = PHYS_SDRAM_1_SIZE;
76 int dram_init_banksize(void)
78 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
79 gd->bd->bi_dram[0].size = gd->ram_size;
84 void hikey960_sd_init(void)
89 data = readl(SCTRL_SCFPLLCTRL0);
90 data |= SCTRL_SCFPLLCTRL0_FPLL0_EN;
91 writel(data, SCTRL_SCFPLLCTRL0);
94 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) &
97 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79));
99 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
101 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
106 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) &
109 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b));
111 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
113 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
118 writel(0, PINMUX4_SDDET);
121 writel(15 << 4, PINCONF3_SDCLK);
122 writel((1 << 0) | (8 << 4), PINCONF3_SDCMD);
123 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0);
124 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1);
125 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2);
126 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3);
128 /* Set SD clock mux */
130 data = readl(CRG_REG_BASE + 0xb8);
131 data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
132 writel(data, CRG_REG_BASE + 0xb8);
134 data = readl(CRG_REG_BASE + 0xb8);
135 } while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
137 /* Take SD out of reset */
138 writel(1 << 18, CRG_PERRSTDIS4);
140 data = readl(CRG_PERRSTSTAT4);
141 } while ((data & (1 << 18)) == (1 << 18));
143 /* Enable hclk_gate_sd */
144 data = readl(CRG_REG_BASE + 0);
146 writel(data, CRG_REG_BASE + 0);
148 /* Enable clk_andgt_mmc */
149 data = readl(CRG_REG_BASE + 0xf4);
150 data |= ((1 << 3) | (1 << 3 << 16));
151 writel(data, CRG_REG_BASE + 0xf4);
153 /* Enable clk_gate_sd */
154 data = readl(CRG_PEREN4);
156 writel(data, CRG_PEREN4);
158 data = readl(CRG_PERCLKEN4);
159 } while ((data & (1 << 17)) != (1 << 17));
162 static void show_psci_version(void)
164 struct arm_smccc_res res;
166 arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
168 printf("PSCI: v%ld.%ld\n",
169 PSCI_VERSION_MAJOR(res.a0),
170 PSCI_VERSION_MINOR(res.a0));
183 void reset_cpu(ulong addr)