1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Linaro
4 * Peter Griffin <peter.griffin@linaro.org>
9 #include <fdt_support.h>
12 #include <dm/platform_data/serial_pl01x.h>
18 #include <power/hi6553_pmic.h>
19 #include <asm-generic/gpio.h>
20 #include <asm/arch/dwmmc.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/periph.h>
23 #include <asm/arch/pinmux.h>
24 #include <asm/arch/hi6220.h>
25 #include <asm/armv8/mmu.h>
27 /*TODO drop this table in favour of device tree */
28 static const struct hikey_gpio_platdata hi6220_gpio[] = {
29 { 0, HI6220_GPIO_BASE(0)},
30 { 1, HI6220_GPIO_BASE(1)},
31 { 2, HI6220_GPIO_BASE(2)},
32 { 3, HI6220_GPIO_BASE(3)},
33 { 4, HI6220_GPIO_BASE(4)},
34 { 5, HI6220_GPIO_BASE(5)},
35 { 6, HI6220_GPIO_BASE(6)},
36 { 7, HI6220_GPIO_BASE(7)},
37 { 8, HI6220_GPIO_BASE(8)},
38 { 9, HI6220_GPIO_BASE(9)},
39 { 10, HI6220_GPIO_BASE(10)},
40 { 11, HI6220_GPIO_BASE(11)},
41 { 12, HI6220_GPIO_BASE(12)},
42 { 13, HI6220_GPIO_BASE(13)},
43 { 14, HI6220_GPIO_BASE(14)},
44 { 15, HI6220_GPIO_BASE(15)},
45 { 16, HI6220_GPIO_BASE(16)},
46 { 17, HI6220_GPIO_BASE(17)},
47 { 18, HI6220_GPIO_BASE(18)},
48 { 19, HI6220_GPIO_BASE(19)},
52 U_BOOT_DEVICES(hi6220_gpios) = {
53 { "gpio_hi6220", &hi6220_gpio[0] },
54 { "gpio_hi6220", &hi6220_gpio[1] },
55 { "gpio_hi6220", &hi6220_gpio[2] },
56 { "gpio_hi6220", &hi6220_gpio[3] },
57 { "gpio_hi6220", &hi6220_gpio[4] },
58 { "gpio_hi6220", &hi6220_gpio[5] },
59 { "gpio_hi6220", &hi6220_gpio[6] },
60 { "gpio_hi6220", &hi6220_gpio[7] },
61 { "gpio_hi6220", &hi6220_gpio[8] },
62 { "gpio_hi6220", &hi6220_gpio[9] },
63 { "gpio_hi6220", &hi6220_gpio[10] },
64 { "gpio_hi6220", &hi6220_gpio[11] },
65 { "gpio_hi6220", &hi6220_gpio[12] },
66 { "gpio_hi6220", &hi6220_gpio[13] },
67 { "gpio_hi6220", &hi6220_gpio[14] },
68 { "gpio_hi6220", &hi6220_gpio[15] },
69 { "gpio_hi6220", &hi6220_gpio[16] },
70 { "gpio_hi6220", &hi6220_gpio[17] },
71 { "gpio_hi6220", &hi6220_gpio[18] },
72 { "gpio_hi6220", &hi6220_gpio[19] },
75 DECLARE_GLOBAL_DATA_PTR;
77 #if !CONFIG_IS_ENABLED(OF_CONTROL)
79 static const struct pl01x_serial_platdata serial_platdata = {
80 #if CONFIG_CONS_INDEX == 1
81 .base = HI6220_UART0_BASE,
82 #elif CONFIG_CONS_INDEX == 4
83 .base = HI6220_UART3_BASE,
85 #error "Unsupported console index value."
91 U_BOOT_DEVICE(hikey_seriala) = {
92 .name = "serial_pl01x",
93 .platdata = &serial_platdata,
97 static struct mm_region hikey_mem_map[] = {
101 .size = 0x80000000UL,
102 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
103 PTE_BLOCK_INNER_SHARE
105 .virt = 0x80000000UL,
106 .phys = 0x80000000UL,
107 .size = 0x80000000UL,
108 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
109 PTE_BLOCK_NON_SHARE |
110 PTE_BLOCK_PXN | PTE_BLOCK_UXN
112 /* List terminator */
117 struct mm_region *mem_map = hikey_mem_map;
119 #ifdef CONFIG_BOARD_EARLY_INIT_F
120 int board_uart_init(void)
122 switch (CONFIG_CONS_INDEX) {
124 hi6220_pinmux_config(PERIPH_ID_UART0);
127 hi6220_pinmux_config(PERIPH_ID_UART3);
130 debug("%s: Unsupported UART selected\n", __func__);
137 int board_early_init_f(void)
144 struct peri_sc_periph_regs *peri_sc =
145 (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
147 struct alwayson_sc_regs *ao_sc =
148 (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
150 /* status offset from enable reg */
151 #define STAT_EN_OFF 0x2
153 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
157 data = readl(clk_base);
160 writel(bitfield, clk_base);
162 data = readl(clk_base + STAT_EN_OFF);
163 } while ((data & bitfield) == 0);
166 /* status offset from disable reg */
167 #define STAT_DIS_OFF 0x1
169 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
173 data = readl(clk_base);
176 writel(data, clk_base);
178 data = readl(clk_base + STAT_DIS_OFF);
179 } while (data & bitfield);
182 #define EYE_PATTERN 0x70533483
184 int board_usb_init(int index, enum usb_init_type init)
188 /* enable USB clock */
189 hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
191 /* take usb IPs out of reset */
192 writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
193 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
196 data = readl(&peri_sc->rst0_stat);
197 data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
198 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
202 data = readl(&peri_sc->ctrl5);
203 data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
204 data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
206 writel(data, &peri_sc->ctrl5);
210 /* configure USB PHY */
211 data = readl(&peri_sc->ctrl4);
213 /* make PHY out of low power mode */
214 data &= ~PERI_CTRL4_PICO_SIDDQ;
215 data &= ~PERI_CTRL4_PICO_OGDISABLE;
216 data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
217 writel(data, &peri_sc->ctrl4);
219 writel(EYE_PATTERN, &peri_sc->ctrl8);
225 static int config_sd_carddetect(void)
229 /* configure GPIO8 as nopull */
230 writel(0, 0xf8001830);
232 gpio_request(8, "SD CD");
234 gpio_direction_input(8);
235 ret = gpio_get_value(8);
238 printf("%s: SD card present\n", __func__);
242 printf("%s: SD card not present\n", __func__);
247 static void mmc1_init_pll(void)
251 /* select SYSPLL as the source of MMC1 */
252 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
253 writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
255 data = readl(&peri_sc->clk0_sel);
256 } while (!(data & (1 << 11)));
258 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
259 writel(1 << 30, &peri_sc->clk0_sel);
261 data = readl(&peri_sc->clk0_sel);
262 } while (data & (1 << 14));
264 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
266 hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
269 /* 1.2GHz / 50 = 24MHz */
270 writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
271 data = readl(&peri_sc->clkcfg8bit2);
272 } while ((data & 0x31) != 0x31);
275 static void mmc1_reset_clk(void)
279 /* disable mmc1 bus clock */
280 hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
282 /* enable mmc1 bus clock */
283 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
285 /* reset mmc1 clock domain */
286 writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
288 /* bypass mmc1 clock phase */
289 data = readl(&peri_sc->ctrl2);
291 writel(data, &peri_sc->ctrl2);
293 /* disable low power */
294 data = readl(&peri_sc->ctrl13);
296 writel(data, &peri_sc->ctrl13);
298 data = readl(&peri_sc->rst0_stat);
299 } while (!(data & PERI_RST0_MMC1));
301 /* unreset mmc1 clock domain */
302 writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
304 data = readl(&peri_sc->rst0_stat);
305 } while (data & PERI_RST0_MMC1);
308 static void mmc0_reset_clk(void)
312 /* disable mmc0 bus clock */
313 hi6220_clk_disable(PERI_CLK0_MMC0, &peri_sc->clk0_dis);
315 /* enable mmc0 bus clock */
316 hi6220_clk_enable(PERI_CLK0_MMC0, &peri_sc->clk0_en);
318 /* reset mmc0 clock domain */
319 writel(PERI_RST0_MMC0, &peri_sc->rst0_en);
321 /* bypass mmc0 clock phase */
322 data = readl(&peri_sc->ctrl2);
324 writel(data, &peri_sc->ctrl2);
326 /* disable low power */
327 data = readl(&peri_sc->ctrl13);
329 writel(data, &peri_sc->ctrl13);
331 data = readl(&peri_sc->rst0_stat);
332 } while (!(data & PERI_RST0_MMC0));
334 /* unreset mmc0 clock domain */
335 writel(PERI_RST0_MMC0, &peri_sc->rst0_dis);
337 data = readl(&peri_sc->rst0_stat);
338 } while (data & PERI_RST0_MMC0);
342 /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
343 static void hi6220_pmussi_init(void)
347 /* Take PMUSSI out of reset */
348 writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
351 data = readl(&ao_sc->rst4_stat);
352 } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
354 /* set PMU SSI clock latency for read operation */
355 data = readl(&ao_sc->mcu_subsys_ctrl3);
356 data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
357 data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
358 writel(data, &ao_sc->mcu_subsys_ctrl3);
360 /* enable PMUSSI clock */
361 data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
362 ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
364 hi6220_clk_enable(data, &ao_sc->clk5_en);
366 /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
367 gpio_request(0, "PWR_HOLD_GPIO0_0");
368 gpio_direction_output(0, 1);
371 int misc_init_r(void)
383 static int init_dwmmc(void)
389 /* mmc0 pll is already configured by ATF */
391 ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
393 printf("%s: Error configuring pinmux for eMMC (%d)\n"
396 ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
398 printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
401 /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
405 ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
407 printf("%s: Error configuring pinmux for eMMC (%d)\n"
410 config_sd_carddetect();
412 ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
414 printf("%s: Error adding SD port (%d)\n", __func__, ret);
420 /* setup board specific PMIC */
421 int power_init_board(void)
423 /* init the hi6220 pmussi ip */
424 hi6220_pmussi_init();
426 power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
431 int board_mmc_init(bd_t *bis)
435 /* add the eMMC and sd ports */
439 debug("init_dwmmc failed\n");
447 gd->ram_size = PHYS_SDRAM_1_SIZE;
451 int dram_init_banksize(void)
454 * Reserve regions below from DT memory node (which gets generated
455 * by U-Boot from the dram banks in arch_fixup_fdt() before booting
456 * the kernel. This will then match the kernel hikey dts memory node.
458 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
459 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
460 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
461 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
462 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
463 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
466 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
467 gd->bd->bi_dram[0].size = 0x05e00000;
469 gd->bd->bi_dram[1].start = 0x05f00000;
470 gd->bd->bi_dram[1].size = 0x00001000;
472 gd->bd->bi_dram[2].start = 0x05f02000;
473 gd->bd->bi_dram[2].size = 0x00efd000;
475 gd->bd->bi_dram[3].start = 0x06e00000;
476 gd->bd->bi_dram[3].size = 0x0060f000;
478 gd->bd->bi_dram[4].start = 0x07410000;
479 gd->bd->bi_dram[4].size = 0x1aaf0000;
481 gd->bd->bi_dram[5].start = 0x22000000;
482 gd->bd->bi_dram[5].size = 0x1c000000;
487 void reset_cpu(ulong addr)
489 writel(0x48698284, &ao_sc->stat0);