board/gumstix/pepper/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for Gumstix Pepper and AM335x-based boards
   4  *
   5  * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
   6  * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
   7  */
   8
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <spl.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/ddr_defs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc_host_def.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/mem.h>
  21 #include <asm/io.h>
  22 #include <asm/emif.h>
  23 #include <asm/gpio.h>
  24 #include <i2c.h>
  25 #include <miiphy.h>
  26 #include <cpsw.h>
  27 #include <power/tps65217.h>
  28 #include <environment.h>
  29 #include <watchdog.h>
  30 #include "board.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifdef CONFIG_SPL_BUILD
  35 #define OSC     (V_OSCK/1000000)
  36
  37 static const struct ddr_data ddr3_data = {
  38         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  39         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  40         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  41         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  42 };
  43
  44 static const struct cmd_control ddr3_cmd_ctrl_data = {
  45         .cmd0csratio = MT41K256M16HA125E_RATIO,
  46         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  47
  48         .cmd1csratio = MT41K256M16HA125E_RATIO,
  49         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  50
  51         .cmd2csratio = MT41K256M16HA125E_RATIO,
  52         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  53 };
  54
  55 static struct emif_regs ddr3_emif_reg_data = {
  56         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  57         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  58         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  59         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  60         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  61         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  62         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  63 };
  64
  65 const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
  66
  67 const struct ctrl_ioregs ioregs_ddr3 = {
  68         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  69         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  70         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  71         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  72         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  73 };
  74
  75 static const struct ddr_data ddr2_data = {
  76         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  77         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  78         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  79 };
  80
  81 static const struct cmd_control ddr2_cmd_ctrl_data = {
  82         .cmd0csratio = MT47H128M16RT25E_RATIO,
  83
  84         .cmd1csratio = MT47H128M16RT25E_RATIO,
  85
  86         .cmd2csratio = MT47H128M16RT25E_RATIO,
  87 };
  88
  89 static const struct emif_regs ddr2_emif_reg_data = {
  90         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  91         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  92         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  93         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  94         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  95         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  96 };
  97
  98 const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
  99
 100 const struct ctrl_ioregs ioregs_ddr2 = {
 101         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 102         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 103         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 104         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 105         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 106 };
 107
 108 static int read_eeprom(struct pepper_board_id *header)
 109 {
 110         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 111                 return -ENODEV;
 112         }
 113
 114         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
 115                 sizeof(struct pepper_board_id))) {
 116                 return -EIO;
 117         }
 118
 119         return 0;
 120 }
 121
 122 const struct dpll_params *get_dpll_ddr_params(void)
 123 {
 124         struct pepper_board_id header;
 125
 126         enable_i2c0_pin_mux();
 127         i2c_set_bus_num(0);
 128
 129         if (read_eeprom(&header) < 0)
 130                 return &dpll_ddr3;
 131
 132         switch (header.device_vendor) {
 133         case GUMSTIX_PEPPER:
 134                 return &dpll_ddr2;
 135         case GUMSTIX_PEPPER_DVI:
 136                 return &dpll_ddr3;
 137         default:
 138                 return &dpll_ddr3;
 139         }
 140 }
 141
 142 void sdram_init(void)
 143 {
 144         const struct dpll_params *dpll = get_dpll_ddr_params();
 145
 146         /*
 147          * Here we are assuming PLL clock reveals the type of RAM.
 148          * DDR2 = 266
 149          * DDR3 = 400
 150          * Note that DDR3 is the default.
 151          */
 152         if (dpll->m == 266) {
 153                 config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
 154                         &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 155         }
 156         else if (dpll->m == 400) {
 157                 config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
 158                         &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 159         }
 160 }
 161
 162 #ifdef CONFIG_SPL_OS_BOOT
 163 int spl_start_uboot(void)
 164 {
 165         /* break into full u-boot on 'c' */
 166         return serial_tstc() && serial_getc() == 'c';
 167 }
 168 #endif
 169
 170 void set_uart_mux_conf(void)
 171 {
 172         enable_uart0_pin_mux();
 173 }
 174
 175 void set_mux_conf_regs(void)
 176 {
 177         enable_board_pin_mux();
 178 }
 179
 180
 181 #endif
 182
 183 int board_init(void)
 184 {
 185 #if defined(CONFIG_HW_WATCHDOG)
 186         hw_watchdog_init();
 187 #endif
 188
 189         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 190         gpmc_init();
 191
 192         return 0;
 193 }
 194
 195 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 196         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 197 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 198
 199 static void cpsw_control(int enabled)
 200 {
 201         /* VTP can be added here */
 202
 203         return;
 204 }
 205
 206 static struct cpsw_slave_data cpsw_slaves[] = {
 207         {
 208                 .slave_reg_ofs  = 0x208,
 209                 .sliver_reg_ofs = 0xd80,
 210                 .phy_addr       = 0,
 211                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 212         },
 213 };
 214
 215 static struct cpsw_platform_data cpsw_data = {
 216         .mdio_base              = CPSW_MDIO_BASE,
 217         .cpsw_base              = CPSW_BASE,
 218         .mdio_div               = 0xff,
 219         .channels               = 8,
 220         .cpdma_reg_ofs          = 0x800,
 221         .slaves                 = 1,
 222         .slave_data             = cpsw_slaves,
 223         .ale_reg_ofs            = 0xd00,
 224         .ale_entries            = 1024,
 225         .host_port_reg_ofs      = 0x108,
 226         .hw_stats_reg_ofs       = 0x900,
 227         .bd_ram_ofs             = 0x2000,
 228         .mac_control            = (1 << 5),
 229         .control                = cpsw_control,
 230         .host_port_num          = 0,
 231         .version                = CPSW_CTRL_VERSION_2,
 232 };
 233
 234 int board_eth_init(bd_t *bis)
 235 {
 236         int rv, n = 0;
 237         uint8_t mac_addr[6];
 238         uint32_t mac_hi, mac_lo;
 239         const char *devname;
 240
 241         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 242                 /* try reading mac address from efuse */
 243                 mac_lo = readl(&cdev->macid0l);
 244                 mac_hi = readl(&cdev->macid0h);
 245                 mac_addr[0] = mac_hi & 0xFF;
 246                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 247                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 248                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 249                 mac_addr[4] = mac_lo & 0xFF;
 250                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 251                 if (is_valid_ethaddr(mac_addr))
 252                         eth_env_set_enetaddr("ethaddr", mac_addr);
 253         }
 254
 255         writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 256
 257         rv = cpsw_register(&cpsw_data);
 258         if (rv < 0)
 259                 printf("Error %d registering CPSW switch\n", rv);
 260         else
 261                 n += rv;
 262
 263         /*
 264          *
 265          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 266          * operating points.  So we must set the TX clock delay feature
 267          * in the KSZ9021 PHY.  Since we only support a single ethernet
 268          * device in U-Boot, we only do this for the current instance.
 269          */
 270         devname = miiphy_get_current_dev();
 271         /* max rx/tx clock delay, min rx/tx control delay */
 272         miiphy_write(devname, 0x0, 0x0b, 0x8104);
 273         miiphy_write(devname, 0x0, 0xc, 0xa0a0);
 274
 275         /* min rx data delay */
 276         miiphy_write(devname, 0x0, 0x0b, 0x8105);
 277         miiphy_write(devname, 0x0, 0x0c, 0x0000);
 278
 279         /* min tx data delay */
 280         miiphy_write(devname, 0x0, 0x0b, 0x8106);
 281         miiphy_write(devname, 0x0, 0x0c, 0x0000);
 282
 283         return n;
 284 }
 285 #endif