1 // SPDX-License-Identifier: GPL-2.0+
4 * Gumstix Inc. <www.gumstix.com>
5 * Maintainer: Ash Charles <ash@gumstix.com>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/mmc_host_def.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
18 #include <asm/mach-types.h>
19 #include <linux/delay.h>
21 #include "duovero_mux_data.h"
25 #if defined(CONFIG_CMD_NET)
26 #define SMSC_NRESET 45
27 static void setup_net_chip(void);
30 #ifdef CONFIG_USB_EHCI_HCD
32 #include <asm/arch/ehci.h>
33 #include <asm/ehci-omap.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 const struct omap_sysinfo sysinfo = {
42 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
53 gd->bd->bi_arch_number = MACH_TYPE_DUOVERO;
54 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
60 * @brief misc_init_r - Configure board specific configurations
61 * such as power configurations, ethernet initialization as phase2 of
71 /* wifi setup: first enable 32Khz clock from 6030 pmic */
73 ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
75 printf("Failed to enable 32Khz clock to wifi module\n");
77 /* then setup WIFI_EN as an output pin and send reset pulse */
78 if (!gpio_request(WIFI_EN, "")) {
79 gpio_direction_output(WIFI_EN, 0);
80 gpio_set_value(WIFI_EN, 1);
82 gpio_set_value(WIFI_EN, 0);
84 gpio_set_value(WIFI_EN, 1);
87 #if defined(CONFIG_CMD_NET)
93 void set_muxconf_regs(void)
95 do_set_mux((*ctrl)->control_padconf_core_base,
96 core_padconf_array_essential,
97 sizeof(core_padconf_array_essential) /
98 sizeof(struct pad_conf_entry));
100 do_set_mux((*ctrl)->control_padconf_wkup_base,
101 wkup_padconf_array_essential,
102 sizeof(wkup_padconf_array_essential) /
103 sizeof(struct pad_conf_entry));
105 do_set_mux((*ctrl)->control_padconf_core_base,
106 core_padconf_array_non_essential,
107 sizeof(core_padconf_array_non_essential) /
108 sizeof(struct pad_conf_entry));
110 do_set_mux((*ctrl)->control_padconf_wkup_base,
111 wkup_padconf_array_non_essential,
112 sizeof(wkup_padconf_array_non_essential) /
113 sizeof(struct pad_conf_entry));
116 #if defined(CONFIG_MMC)
117 int board_mmc_init(bd_t *bis)
119 return omap_mmc_init(0, 0, 0, -1, -1);
122 #if !defined(CONFIG_SPL_BUILD)
123 void board_mmc_power_init(void)
125 twl6030_power_mmc_init(0);
130 #if defined(CONFIG_CMD_NET)
132 #define GPMC_SIZE_16M 0xF
133 #define GPMC_BASEADDR_MASK 0x3F
134 #define GPMC_CS_ENABLE 0x1
136 static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
139 writel(0, &cs->config7);
141 /* Delay for settling */
142 writel(gpmc_config[0], &cs->config1);
143 writel(gpmc_config[1], &cs->config2);
144 writel(gpmc_config[2], &cs->config3);
145 writel(gpmc_config[3], &cs->config4);
146 writel(gpmc_config[4], &cs->config5);
147 writel(gpmc_config[5], &cs->config6);
150 * Enable the config. size is the CS size and goes in
151 * bits 11:8. We set bit 6 to enable this CS and the base
152 * address goes into bits 5:0.
154 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
155 ((base >> 24) & GPMC_BASEADDR_MASK),
161 /* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
162 #define NET_LAN9221_GPMC_CONFIG1 0x2a001203
163 #define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
164 #define NET_LAN9221_GPMC_CONFIG3 0x00020200
165 #define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
166 #define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
167 #define NET_LAN9221_GPMC_CONFIG6 0x8a070707
168 #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
170 /* GPMC definitions for LAN9221 chips on expansion boards */
171 static const u32 gpmc_lan_config[] = {
172 NET_LAN9221_GPMC_CONFIG1,
173 NET_LAN9221_GPMC_CONFIG2,
174 NET_LAN9221_GPMC_CONFIG3,
175 NET_LAN9221_GPMC_CONFIG4,
176 NET_LAN9221_GPMC_CONFIG5,
177 NET_LAN9221_GPMC_CONFIG6,
178 /*CONFIG7- computed as params */
182 * Routine: setup_net_chip
183 * Description: Setting up the configuration GPMC registers specific to the
186 static void setup_net_chip(void)
188 enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
191 /* Make GPIO SMSC_NRESET as output pin and send reset pulse */
192 if (!gpio_request(SMSC_NRESET, "")) {
193 gpio_direction_output(SMSC_NRESET, 0);
194 gpio_set_value(SMSC_NRESET, 1);
196 gpio_set_value(SMSC_NRESET, 0);
198 gpio_set_value(SMSC_NRESET, 1);
203 int board_eth_init(bd_t *bis)
206 #ifdef CONFIG_SMC911X
207 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
212 #ifdef CONFIG_USB_EHCI_HCD
214 static struct omap_usbhs_board_data usbhs_bdata = {
215 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
216 .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
217 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
220 int ehci_hcd_init(int index, enum usb_init_type init,
221 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
224 unsigned int utmi_clk;
225 u32 auxclk, altclksrc;
227 /* Now we can enable our port clocks */
228 utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
229 utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
230 setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
232 auxclk = readl(&scrm->auxclk3);
234 auxclk &= ~AUXCLK_SRCSELECT_MASK;
235 auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
236 /* Set the divisor to 2 */
237 auxclk &= ~AUXCLK_CLKDIV_MASK;
238 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
239 /* Request auxilary clock #3 */
240 auxclk |= AUXCLK_ENABLE_MASK;
241 writel(auxclk, &scrm->auxclk3);
243 altclksrc = readl(&scrm->altclksrc);
245 /* Activate alternate system clock supplier */
246 altclksrc &= ~ALTCLKSRC_MODE_MASK;
247 altclksrc |= ALTCLKSRC_MODE_ACTIVE;
250 altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
252 writel(altclksrc, &scrm->altclksrc);
254 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
261 int ehci_hcd_stop(int index)
263 return omap_ehci_hcd_stop();
268 * get_board_rev() - get board revision
270 u32 get_board_rev(void)