1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Google, Inc
11 #include <asm/arch-rockchip/clock.h>
12 #include <dt-bindings/clock/rk3288-cru.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <power/regulator.h>
18 * We should increase the DDR voltage to 1.2V using the PWM regulator.
19 * There is a U-Boot driver for this but it may need to add support for the
20 * 'voltage-table' property.
22 #ifndef CONFIG_SPL_BUILD
23 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
24 static int veyron_init(void)
30 ret = regulator_get_by_platname("vdd_arm", &dev);
32 debug("Cannot set regulator name\n");
36 /* Slowly raise to max CPU voltage to prevent overshoot */
37 ret = regulator_set_value(dev, 1200000);
40 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
41 ret = regulator_set_value(dev, 1400000);
44 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
46 ret = rockchip_get_clk(&clk.dev);
50 ret = clk_set_rate(&clk, 1800000000);
51 if (IS_ERR_VALUE(ret))
54 ret = regulator_get_by_platname("vcc33_sd", &dev);
56 debug("Cannot get regulator name\n");
60 ret = regulator_set_value(dev, 3300000);
64 ret = regulators_enable_boot_on(false);
66 debug("%s: Cannot enable boot on regulators\n", __func__);
74 int board_early_init_f(void)
79 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
80 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
87 * This init is done in SPL, but when chain-loading U-Boot SPL will
88 * have been skipped. Allow the clock driver to check if it needs
91 ret = rockchip_get_clk(&dev);
93 debug("CLK init failed: %d\n", ret);