board/google/imx8mq_phanbell/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2020 NXP
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <hang.h>
   9 #include <asm/io.h>
  10 #include <errno.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/ddr.h>
  15 #include <asm/arch/imx8mq_pins.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/gpio.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/sections.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <mmc.h>
  24 #include <spl.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static void spl_dram_init(void)
  29 {
  30         /* ddr init */
  31         ddr_init(&dram_timing);
  32 }
  33
  34 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 12)
  35 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
  36 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  37
  38 int board_mmc_getcd(struct mmc *mmc)
  39 {
  40         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  41         int ret = 0;
  42
  43         switch (cfg->esdhc_base) {
  44         case USDHC1_BASE_ADDR:
  45                 ret = 1;
  46                 break;
  47         case USDHC2_BASE_ADDR:
  48                 ret = !gpio_get_value(USDHC2_CD_GPIO);
  49                 return ret;
  50         }
  51
  52         return 1;
  53 }
  54
  55 #define USDHC_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
  56                          PAD_CTL_FSEL2)
  57 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
  58
  59 static iomux_v3_cfg_t const usdhc1_pads[] = {
  60         IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61         IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62         IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63         IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64         IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65         IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66         IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67         IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  71 };
  72
  73 static iomux_v3_cfg_t const usdhc2_pads[] = {
  74         IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  75         IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  76         IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  77         IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  78         IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
  79         IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  80         IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  81         IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  82 };
  83
  84 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  85         {USDHC1_BASE_ADDR},
  86         {USDHC2_BASE_ADDR},
  87 };
  88
  89 int board_mmc_init(bd_t *bis)
  90 {
  91         int i, ret;
  92         /*
  93          * According to the board_mmc_init() the following map is done:
  94          * (U-Boot device node)    (Physical Port)
  95          * mmc0                    USDHC1
  96          * mmc1                    USDHC2
  97          */
  98         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  99                 switch (i) {
 100                 case 0:
 101                         init_clk_usdhc(0);
 102                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
 103                         usdhc_cfg[0].max_bus_width = 8;
 104                         imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 105                                                          ARRAY_SIZE(usdhc1_pads));
 106                         gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
 107                         gpio_direction_output(USDHC1_PWR_GPIO, 0);
 108                         udelay(500);
 109                         gpio_direction_output(USDHC1_PWR_GPIO, 1);
 110                         break;
 111                 case 1:
 112                         init_clk_usdhc(1);
 113                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
 114                         usdhc_cfg[1].max_bus_width = 4;
 115                         imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 116                                                          ARRAY_SIZE(usdhc2_pads));
 117                         gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
 118                         gpio_direction_output(USDHC2_PWR_GPIO, 0);
 119                         udelay(500);
 120                         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 121                         break;
 122                 default:
 123                         printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
 124                         return -EINVAL;
 125                 }
 126
 127                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 128                 if (ret)
 129                         return ret;
 130         }
 131
 132         return 0;
 133 }
 134
 135 void spl_board_init(void)
 136 {
 137         puts("Normal Boot\n");
 138 }
 139
 140 #ifdef CONFIG_SPL_LOAD_FIT
 141 int board_fit_config_name_match(const char *name)
 142 {
 143         /* Just empty function now - can't decide what to choose */
 144         debug("%s: %s\n", __func__, name);
 145
 146         return 0;
 147 }
 148 #endif
 149
 150 void board_init_f(ulong dummy)
 151 {
 152         int ret;
 153
 154         /* Clear global data */
 155         memset((void *)gd, 0, sizeof(gd_t));
 156
 157         arch_cpu_init();
 158
 159         init_uart_clk(0);
 160
 161         board_early_init_f();
 162
 163         timer_init();
 164
 165         preloader_console_init();
 166
 167         /* Clear the BSS. */
 168         memset(__bss_start, 0, __bss_end - __bss_start);
 169
 170         ret = spl_init();
 171         if (ret) {
 172                 debug("spl_init() failed: %d\n", ret);
 173                 hang();
 174         }
 175
 176         enable_tzc380();
 177
 178         /* DDR initialization */
 179         spl_dram_init();
 180
 181         board_init_r(NULL, 0);
 182 }