board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <image.h>
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <env.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/libfdt.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <miiphy.h>
  25 #include <net.h>
  26 #include <netdev.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <power/regulator.h>
  32 #include <power/da9063_pmic.h>
  33 #include <input.h>
  34 #include <pwm.h>
  35 #include <version.h>
  36 #include <stdlib.h>
  37 #include <dm/root.h>
  38 #include "../common/ge_common.h"
  39 #include "../common/vpd_reader.h"
  40 #include "../../../drivers/net/e1000.h"
  41 #include <pci.h>
  42 #include <panel.h>
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 static int confidx;  /* Default to generic. */
  47 static struct vpd_cache vpd;
  48
  49 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  51         PAD_CTL_HYS)
  52
  53 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  54         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  55
  56 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  57         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  58
  59 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  60         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  61
  62 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  64         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  65
  66 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  67
  68 int dram_init(void)
  69 {
  70         gd->ram_size = imx_ddr_size();
  71
  72         return 0;
  73 }
  74
  75 static int mx6_rgmii_rework(struct phy_device *phydev)
  76 {
  77         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  78         /* set device address 0x7 */
  79         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  80         /* offset 0x8016: CLK_25M Clock Select */
  81         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  82         /* enable register write, no post increment, address 0x7 */
  83         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  84         /* set to 125 MHz from local PLL source */
  85         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  86
  87         /* rgmii tx clock delay enable */
  88         /* set debug port address: SerDes Test and System Mode Control */
  89         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  90         /* enable rgmii tx clock delay */
  91         /* set the reserved bits to avoid board specific voltage peak issue*/
  92         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  93
  94         return 0;
  95 }
  96
  97 int board_phy_config(struct phy_device *phydev)
  98 {
  99         mx6_rgmii_rework(phydev);
 100
 101         if (phydev->drv->config)
 102                 phydev->drv->config(phydev);
 103
 104         return 0;
 105 }
 106
 107 #if defined(CONFIG_VIDEO_IPUV3)
 108 static void do_enable_backlight(struct display_info_t const *dev)
 109 {
 110         struct udevice *panel;
 111         int ret;
 112
 113         ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
 114         if (ret) {
 115                 printf("Could not find panel: %d\n", ret);
 116                 return;
 117         }
 118
 119         panel_set_backlight(panel, 100);
 120         panel_enable_backlight(panel);
 121 }
 122
 123 static void do_enable_hdmi(struct display_info_t const *dev)
 124 {
 125         imx_enable_hdmi_phy();
 126 }
 127
 128 static int is_b850v3(void)
 129 {
 130         return confidx == 3;
 131 }
 132
 133 static int detect_lcd(struct display_info_t const *dev)
 134 {
 135         return !is_b850v3();
 136 }
 137
 138 struct display_info_t const displays[] = {{
 139         .bus    = -1,
 140         .addr   = -1,
 141         .pixfmt = IPU_PIX_FMT_RGB24,
 142         .detect = detect_lcd,
 143         .enable = do_enable_backlight,
 144         .mode   = {
 145                 .name           = "G121X1-L03",
 146                 .refresh        = 60,
 147                 .xres           = 1024,
 148                 .yres           = 768,
 149                 .pixclock       = 15385,
 150                 .left_margin    = 20,
 151                 .right_margin   = 300,
 152                 .upper_margin   = 30,
 153                 .lower_margin   = 8,
 154                 .hsync_len      = 1,
 155                 .vsync_len      = 1,
 156                 .sync           = FB_SYNC_EXT,
 157                 .vmode          = FB_VMODE_NONINTERLACED
 158 } }, {
 159         .bus    = -1,
 160         .addr   = 3,
 161         .pixfmt = IPU_PIX_FMT_RGB24,
 162         .detect = detect_hdmi,
 163         .enable = do_enable_hdmi,
 164         .mode   = {
 165                 .name           = "HDMI",
 166                 .refresh        = 60,
 167                 .xres           = 1024,
 168                 .yres           = 768,
 169                 .pixclock       = 15385,
 170                 .left_margin    = 220,
 171                 .right_margin   = 40,
 172                 .upper_margin   = 21,
 173                 .lower_margin   = 7,
 174                 .hsync_len      = 60,
 175                 .vsync_len      = 10,
 176                 .sync           = FB_SYNC_EXT,
 177                 .vmode          = FB_VMODE_NONINTERLACED
 178 } } };
 179 size_t display_count = ARRAY_SIZE(displays);
 180
 181 static void enable_videopll(void)
 182 {
 183         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 184         s32 timeout = 100000;
 185
 186         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 187
 188         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 189          *   |
 190          * PLL5
 191          *   |
 192          * CS2CDR[LDB_DI0_CLK_SEL]
 193          *   |
 194          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 195          *   |
 196          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 197          */
 198
 199         clrsetbits_le32(&ccm->analog_pll_video,
 200                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 201                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 202                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 203                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 204
 205         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 206         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 207
 208         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 209
 210         while (timeout--)
 211                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 212                         break;
 213
 214         if (timeout < 0)
 215                 printf("Warning: video pll lock timeout!\n");
 216
 217         clrsetbits_le32(&ccm->analog_pll_video,
 218                         BM_ANADIG_PLL_VIDEO_BYPASS,
 219                         BM_ANADIG_PLL_VIDEO_ENABLE);
 220 }
 221
 222 static void setup_display_b850v3(void)
 223 {
 224         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 225         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 226
 227         enable_videopll();
 228
 229         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 230         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 231
 232         imx_setup_hdmi();
 233
 234         /* Set LDB_DI0 as clock source for IPU_DI0 */
 235         clrsetbits_le32(&mxc_ccm->chsccdr,
 236                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 237                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 238                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 239
 240         /* Turn on IPU LDB DI0 clocks */
 241         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 242
 243         enable_ipu_clock();
 244
 245         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 246                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 247                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 248                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 249                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 250                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 251                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 252                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 253                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 254                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 255                &iomux->gpr[2]);
 256
 257         clrbits_le32(&iomux->gpr[3],
 258                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 259                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 260                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 261 }
 262
 263 static void setup_display_bx50v3(void)
 264 {
 265         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 266         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 267
 268         enable_videopll();
 269
 270         /* When a reset/reboot is performed the display power needs to be turned
 271          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 272          * an additional 200ms here. Unfortunately we use external PMIC for
 273          * doing the reset, so can not differentiate between POR vs soft reset
 274          */
 275         mdelay(200);
 276
 277         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 278         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 279
 280         /* Set LDB_DI0 as clock source for IPU_DI0 */
 281         clrsetbits_le32(&mxc_ccm->chsccdr,
 282                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 283                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 284                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 285
 286         /* Turn on IPU LDB DI0 clocks */
 287         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 288
 289         enable_ipu_clock();
 290
 291         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 292                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 293                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 294                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 295                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 296                &iomux->gpr[2]);
 297
 298         clrsetbits_le32(&iomux->gpr[3],
 299                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 300                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 301                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 302 }
 303 #endif /* CONFIG_VIDEO_IPUV3 */
 304
 305 /*
 306  * Do not overwrite the console
 307  * Use always serial for U-Boot console
 308  */
 309 int overwrite_console(void)
 310 {
 311         return 1;
 312 }
 313
 314 #define VPD_TYPE_INVALID 0x00
 315 #define VPD_BLOCK_NETWORK 0x20
 316 #define VPD_BLOCK_HWID 0x44
 317 #define VPD_PRODUCT_B850 1
 318 #define VPD_PRODUCT_B650 2
 319 #define VPD_PRODUCT_B450 3
 320 #define VPD_HAS_MAC1 0x1
 321 #define VPD_HAS_MAC2 0x2
 322 #define VPD_MAC_ADDRESS_LENGTH 6
 323
 324 struct vpd_cache {
 325         bool is_read;
 326         u8 product_id;
 327         u8 has;
 328         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 329         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 330 };
 331
 332 /*
 333  * Extracts MAC and product information from the VPD.
 334  */
 335 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 336                         size_t size, u8 const *data)
 337 {
 338         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 339             size >= 1) {
 340                 vpd->product_id = data[0];
 341         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 342                    type != VPD_TYPE_INVALID) {
 343                 if (size >= 6) {
 344                         vpd->has |= VPD_HAS_MAC1;
 345                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 346                 }
 347                 if (size >= 12) {
 348                         vpd->has |= VPD_HAS_MAC2;
 349                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 350                 }
 351         }
 352
 353         return 0;
 354 }
 355
 356 static void process_vpd(struct vpd_cache *vpd)
 357 {
 358         int fec_index = 0;
 359         int i210_index = -1;
 360
 361         if (!vpd->is_read) {
 362                 printf("VPD wasn't read");
 363                 return;
 364         }
 365
 366         if (vpd->has & VPD_HAS_MAC1)
 367                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 368
 369         env_set("ethact", "eth0");
 370
 371         switch (vpd->product_id) {
 372         case VPD_PRODUCT_B450:
 373                 env_set("confidx", "1");
 374                 i210_index = 1;
 375                 break;
 376         case VPD_PRODUCT_B650:
 377                 env_set("confidx", "2");
 378                 i210_index = 1;
 379                 break;
 380         case VPD_PRODUCT_B850:
 381                 env_set("confidx", "3");
 382                 i210_index = 2;
 383                 break;
 384         }
 385
 386         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 387                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 388 }
 389
 390 static iomux_v3_cfg_t const misc_pads[] = {
 391         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 392         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 393         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 394         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 395         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 396         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 397         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 398         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 399 };
 400 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 401 #define WIFI_EN IMX_GPIO_NR(6, 14)
 402
 403 int board_early_init_f(void)
 404 {
 405         imx_iomux_v3_setup_multiple_pads(misc_pads,
 406                                          ARRAY_SIZE(misc_pads));
 407
 408 #if defined(CONFIG_VIDEO_IPUV3)
 409         /* Set LDB clock to Video PLL */
 410         select_ldb_di_clock_source(MXC_PLL5_CLK);
 411 #endif
 412         return 0;
 413 }
 414
 415 static void set_confidx(const struct vpd_cache* vpd)
 416 {
 417         switch (vpd->product_id) {
 418         case VPD_PRODUCT_B450:
 419                 confidx = 1;
 420                 break;
 421         case VPD_PRODUCT_B650:
 422                 confidx = 2;
 423                 break;
 424         case VPD_PRODUCT_B850:
 425                 confidx = 3;
 426                 break;
 427         }
 428 }
 429
 430 int board_init(void)
 431 {
 432         if (!read_vpd(&vpd, vpd_callback)) {
 433                 int ret, rescan;
 434
 435                 vpd.is_read = true;
 436                 set_confidx(&vpd);
 437
 438                 ret = fdtdec_resetup(&rescan);
 439                 if (!ret && rescan) {
 440                         dm_uninit();
 441                         dm_init_and_scan(false);
 442                 }
 443         }
 444
 445         gpio_request(SUS_S3_OUT, "sus_s3_out");
 446         gpio_direction_output(SUS_S3_OUT, 1);
 447
 448         gpio_request(WIFI_EN, "wifi_en");
 449         gpio_direction_output(WIFI_EN, 1);
 450
 451 #if defined(CONFIG_VIDEO_IPUV3)
 452         if (is_b850v3())
 453                 setup_display_b850v3();
 454         else
 455                 setup_display_bx50v3();
 456 #endif
 457
 458         /* address of boot parameters */
 459         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 460
 461         return 0;
 462 }
 463
 464 #ifdef CONFIG_CMD_BMODE
 465 static const struct boot_mode board_boot_modes[] = {
 466         /* 4 bit bus width */
 467         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 468         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 469         {NULL,   0},
 470 };
 471 #endif
 472
 473 void pmic_init(void)
 474 {
 475         struct udevice *reg;
 476         int ret, i;
 477         static const char * const bucks[] = {
 478                 "bcore1",
 479                 "bcore2",
 480                 "bpro",
 481                 "bmem",
 482                 "bio",
 483                 "bperi",
 484         };
 485
 486         for (i = 0; i < ARRAY_SIZE(bucks); i++) {
 487                 ret = regulator_get_by_devname(bucks[i], &reg);
 488                 if (reg < 0) {
 489                         printf("%s(): Unable to get regulator %s: %d\n",
 490                                __func__, bucks[i], ret);
 491                         continue;
 492                 }
 493                 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
 494         }
 495 }
 496
 497 int board_late_init(void)
 498 {
 499         process_vpd(&vpd);
 500
 501 #ifdef CONFIG_CMD_BMODE
 502         add_board_boot_modes(board_boot_modes);
 503 #endif
 504
 505         if (is_b850v3())
 506                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 507         else
 508                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 509
 510         /* board specific pmic init */
 511         pmic_init();
 512
 513         check_time();
 514
 515         pci_init();
 516
 517         return 0;
 518 }
 519
 520 /*
 521  * Removes the 'eth[0-9]*addr' environment variable with the given index
 522  *
 523  * @param index [in] the index of the eth_device whose variable is to be removed
 524  */
 525 static void remove_ethaddr_env_var(int index)
 526 {
 527         char env_var_name[9];
 528
 529         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 530         env_set(env_var_name, NULL);
 531 }
 532
 533 int last_stage_init(void)
 534 {
 535         int i;
 536
 537         /*
 538          * Remove first three ethaddr which may have been created by
 539          * function process_vpd().
 540          */
 541         for (i = 0; i < 3; ++i)
 542                 remove_ethaddr_env_var(i);
 543
 544         return 0;
 545 }
 546
 547 int checkboard(void)
 548 {
 549         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 550         return 0;
 551 }
 552
 553 #ifdef CONFIG_OF_BOARD_SETUP
 554 int ft_board_setup(void *blob, bd_t *bd)
 555 {
 556         char *rtc_status = env_get("rtc_status");
 557
 558         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 559                     strlen(version_string) + 1);
 560
 561         fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
 562                     strlen(rtc_status) + 1);
 563         return 0;
 564 }
 565 #endif
 566
 567 int board_fit_config_name_match(const char *name)
 568 {
 569         if (!vpd.is_read)
 570                 return strcmp(name, "imx6q-bx50v3");
 571
 572         switch (vpd.product_id) {
 573         case VPD_PRODUCT_B450:
 574                 return strcmp(name, "imx6q-b450v3");
 575         case VPD_PRODUCT_B650:
 576                 return strcmp(name, "imx6q-b650v3");
 577         case VPD_PRODUCT_B850:
 578                 return strcmp(name, "imx6q-b850v3");
 579         default:
 580                 return -1;
 581         }
 582 }
 583
 584 int embedded_dtb_select(void)
 585 {
 586         vpd.is_read = false;
 587         return fdtdec_setup();
 588 }