board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <env.h>
  13 #include <linux/errno.h>
  14 #include <linux/libfdt.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/mxc_i2c.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <miiphy.h>
  23 #include <net.h>
  24 #include <netdev.h>
  25 #include <asm/arch/mxc_hdmi.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <i2c.h>
  30 #include <input.h>
  31 #include <pwm.h>
  32 #include <version.h>
  33 #include <stdlib.h>
  34 #include "../common/ge_common.h"
  35 #include "../common/vpd_reader.h"
  36 #include "../../../drivers/net/e1000.h"
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 static int confidx = 3;  /* Default to b850v3. */
  40 static struct vpd_cache vpd;
  41
  42 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  44         PAD_CTL_HYS)
  45
  46 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  51         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  52
  53 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  54         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  55
  56 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  57         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  58
  59 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  62
  63 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  64
  65 int dram_init(void)
  66 {
  67         gd->ram_size = imx_ddr_size();
  68
  69         return 0;
  70 }
  71
  72 static iomux_v3_cfg_t const uart3_pads[] = {
  73         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  74         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  75         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  76         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77 };
  78
  79 static iomux_v3_cfg_t const uart4_pads[] = {
  80         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 static iomux_v3_cfg_t const enet_pads[] = {
  85         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  94         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  95         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  96         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  97         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  98         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  99         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 100         /* AR8033 PHY Reset */
 101         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 102 };
 103
 104 static void setup_iomux_enet(void)
 105 {
 106         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 107
 108         /* Reset AR8033 PHY */
 109         gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
 110         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 111         mdelay(10);
 112         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 113         mdelay(1);
 114 }
 115
 116 static struct i2c_pads_info i2c_pad_info1 = {
 117         .scl = {
 118                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 119                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 120                 .gp = IMX_GPIO_NR(5, 27)
 121         },
 122         .sda = {
 123                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 124                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 125                 .gp = IMX_GPIO_NR(5, 26)
 126         }
 127 };
 128
 129 static struct i2c_pads_info i2c_pad_info2 = {
 130         .scl = {
 131                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 132                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 133                 .gp = IMX_GPIO_NR(4, 12)
 134         },
 135         .sda = {
 136                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 137                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 138                 .gp = IMX_GPIO_NR(4, 13)
 139         }
 140 };
 141
 142 static struct i2c_pads_info i2c_pad_info3 = {
 143         .scl = {
 144                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 145                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 146                 .gp = IMX_GPIO_NR(1, 3)
 147         },
 148         .sda = {
 149                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 150                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 151                 .gp = IMX_GPIO_NR(1, 6)
 152         }
 153 };
 154
 155 static iomux_v3_cfg_t const pcie_pads[] = {
 156         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 157         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 158 };
 159
 160 static void setup_pcie(void)
 161 {
 162         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 163 }
 164
 165 static void setup_iomux_uart(void)
 166 {
 167         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 168         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 169 }
 170
 171 static int mx6_rgmii_rework(struct phy_device *phydev)
 172 {
 173         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 174         /* set device address 0x7 */
 175         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 176         /* offset 0x8016: CLK_25M Clock Select */
 177         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 178         /* enable register write, no post increment, address 0x7 */
 179         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 180         /* set to 125 MHz from local PLL source */
 181         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 182
 183         /* rgmii tx clock delay enable */
 184         /* set debug port address: SerDes Test and System Mode Control */
 185         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 186         /* enable rgmii tx clock delay */
 187         /* set the reserved bits to avoid board specific voltage peak issue*/
 188         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 189
 190         return 0;
 191 }
 192
 193 int board_phy_config(struct phy_device *phydev)
 194 {
 195         mx6_rgmii_rework(phydev);
 196
 197         if (phydev->drv->config)
 198                 phydev->drv->config(phydev);
 199
 200         return 0;
 201 }
 202
 203 #if defined(CONFIG_VIDEO_IPUV3)
 204 static iomux_v3_cfg_t const backlight_pads[] = {
 205         /* Power for LVDS Display */
 206         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 207 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 208         /* Backlight enable for LVDS display */
 209         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 210 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 211         /* backlight PWM brightness control */
 212         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 213 };
 214
 215 static void do_enable_hdmi(struct display_info_t const *dev)
 216 {
 217         imx_enable_hdmi_phy();
 218 }
 219
 220 int board_cfb_skip(void)
 221 {
 222         gpio_direction_output(LVDS_POWER_GP, 1);
 223
 224         return 0;
 225 }
 226
 227 static int is_b850v3(void)
 228 {
 229         return confidx == 3;
 230 }
 231
 232 static int detect_lcd(struct display_info_t const *dev)
 233 {
 234         return !is_b850v3();
 235 }
 236
 237 struct display_info_t const displays[] = {{
 238         .bus    = -1,
 239         .addr   = -1,
 240         .pixfmt = IPU_PIX_FMT_RGB24,
 241         .detect = detect_lcd,
 242         .enable = NULL,
 243         .mode   = {
 244                 .name           = "G121X1-L03",
 245                 .refresh        = 60,
 246                 .xres           = 1024,
 247                 .yres           = 768,
 248                 .pixclock       = 15385,
 249                 .left_margin    = 20,
 250                 .right_margin   = 300,
 251                 .upper_margin   = 30,
 252                 .lower_margin   = 8,
 253                 .hsync_len      = 1,
 254                 .vsync_len      = 1,
 255                 .sync           = FB_SYNC_EXT,
 256                 .vmode          = FB_VMODE_NONINTERLACED
 257 } }, {
 258         .bus    = -1,
 259         .addr   = 3,
 260         .pixfmt = IPU_PIX_FMT_RGB24,
 261         .detect = detect_hdmi,
 262         .enable = do_enable_hdmi,
 263         .mode   = {
 264                 .name           = "HDMI",
 265                 .refresh        = 60,
 266                 .xres           = 1024,
 267                 .yres           = 768,
 268                 .pixclock       = 15385,
 269                 .left_margin    = 220,
 270                 .right_margin   = 40,
 271                 .upper_margin   = 21,
 272                 .lower_margin   = 7,
 273                 .hsync_len      = 60,
 274                 .vsync_len      = 10,
 275                 .sync           = FB_SYNC_EXT,
 276                 .vmode          = FB_VMODE_NONINTERLACED
 277 } } };
 278 size_t display_count = ARRAY_SIZE(displays);
 279
 280 static void enable_videopll(void)
 281 {
 282         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 283         s32 timeout = 100000;
 284
 285         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 286
 287         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 288          *   |
 289          * PLL5
 290          *   |
 291          * CS2CDR[LDB_DI0_CLK_SEL]
 292          *   |
 293          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 294          *   |
 295          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 296          */
 297
 298         clrsetbits_le32(&ccm->analog_pll_video,
 299                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 300                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 301                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 302                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 303
 304         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 305         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 306
 307         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 308
 309         while (timeout--)
 310                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 311                         break;
 312
 313         if (timeout < 0)
 314                 printf("Warning: video pll lock timeout!\n");
 315
 316         clrsetbits_le32(&ccm->analog_pll_video,
 317                         BM_ANADIG_PLL_VIDEO_BYPASS,
 318                         BM_ANADIG_PLL_VIDEO_ENABLE);
 319 }
 320
 321 static void setup_display_b850v3(void)
 322 {
 323         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 324         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 325
 326         enable_videopll();
 327
 328         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 329         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 330
 331         imx_setup_hdmi();
 332
 333         /* Set LDB_DI0 as clock source for IPU_DI0 */
 334         clrsetbits_le32(&mxc_ccm->chsccdr,
 335                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 336                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 337                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 338
 339         /* Turn on IPU LDB DI0 clocks */
 340         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 341
 342         enable_ipu_clock();
 343
 344         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 345                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 346                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 347                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 348                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 349                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 350                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 351                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 352                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 353                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 354                &iomux->gpr[2]);
 355
 356         clrbits_le32(&iomux->gpr[3],
 357                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 358                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 359                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 360 }
 361
 362 static void setup_display_bx50v3(void)
 363 {
 364         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 365         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 366
 367         enable_videopll();
 368
 369         /* When a reset/reboot is performed the display power needs to be turned
 370          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 371          * an additional 200ms here. Unfortunately we use external PMIC for
 372          * doing the reset, so can not differentiate between POR vs soft reset
 373          */
 374         mdelay(200);
 375
 376         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 377         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 378
 379         /* Set LDB_DI0 as clock source for IPU_DI0 */
 380         clrsetbits_le32(&mxc_ccm->chsccdr,
 381                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 382                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 383                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 384
 385         /* Turn on IPU LDB DI0 clocks */
 386         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 387
 388         enable_ipu_clock();
 389
 390         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 391                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 392                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 393                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 394                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 395                &iomux->gpr[2]);
 396
 397         clrsetbits_le32(&iomux->gpr[3],
 398                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 399                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 400                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 401
 402         /* backlights off until needed */
 403         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 404                                          ARRAY_SIZE(backlight_pads));
 405         gpio_request(LVDS_POWER_GP, "lvds_power");
 406         gpio_direction_input(LVDS_POWER_GP);
 407 }
 408 #endif /* CONFIG_VIDEO_IPUV3 */
 409
 410 /*
 411  * Do not overwrite the console
 412  * Use always serial for U-Boot console
 413  */
 414 int overwrite_console(void)
 415 {
 416         return 1;
 417 }
 418
 419 #define VPD_TYPE_INVALID 0x00
 420 #define VPD_BLOCK_NETWORK 0x20
 421 #define VPD_BLOCK_HWID 0x44
 422 #define VPD_PRODUCT_B850 1
 423 #define VPD_PRODUCT_B650 2
 424 #define VPD_PRODUCT_B450 3
 425 #define VPD_HAS_MAC1 0x1
 426 #define VPD_HAS_MAC2 0x2
 427 #define VPD_MAC_ADDRESS_LENGTH 6
 428
 429 struct vpd_cache {
 430         bool is_read;
 431         u8 product_id;
 432         u8 has;
 433         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 434         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 435 };
 436
 437 /*
 438  * Extracts MAC and product information from the VPD.
 439  */
 440 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 441                         size_t size, u8 const *data)
 442 {
 443         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 444             size >= 1) {
 445                 vpd->product_id = data[0];
 446         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 447                    type != VPD_TYPE_INVALID) {
 448                 if (size >= 6) {
 449                         vpd->has |= VPD_HAS_MAC1;
 450                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 451                 }
 452                 if (size >= 12) {
 453                         vpd->has |= VPD_HAS_MAC2;
 454                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 455                 }
 456         }
 457
 458         return 0;
 459 }
 460
 461 static void process_vpd(struct vpd_cache *vpd)
 462 {
 463         int fec_index = -1;
 464         int i210_index = -1;
 465
 466         if (!vpd->is_read) {
 467                 printf("VPD wasn't read");
 468                 return;
 469         }
 470
 471         switch (vpd->product_id) {
 472         case VPD_PRODUCT_B450:
 473                 env_set("confidx", "1");
 474                 i210_index = 0;
 475                 fec_index = 1;
 476                 break;
 477         case VPD_PRODUCT_B650:
 478                 env_set("confidx", "2");
 479                 i210_index = 0;
 480                 fec_index = 1;
 481                 break;
 482         case VPD_PRODUCT_B850:
 483                 env_set("confidx", "3");
 484                 i210_index = 1;
 485                 fec_index = 2;
 486                 break;
 487         }
 488
 489         if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
 490                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 491
 492         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 493                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 494 }
 495
 496 int board_eth_init(bd_t *bis)
 497 {
 498         setup_iomux_enet();
 499         setup_pcie();
 500
 501         e1000_initialize(bis);
 502
 503         return cpu_eth_init(bis);
 504 }
 505
 506 static iomux_v3_cfg_t const misc_pads[] = {
 507         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 508         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 509         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 510         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 511         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 512         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 513         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 514         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 515 };
 516 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 517 #define WIFI_EN IMX_GPIO_NR(6, 14)
 518
 519 int board_early_init_f(void)
 520 {
 521         imx_iomux_v3_setup_multiple_pads(misc_pads,
 522                                          ARRAY_SIZE(misc_pads));
 523
 524         setup_iomux_uart();
 525
 526 #if defined(CONFIG_VIDEO_IPUV3)
 527         /* Set LDB clock to Video PLL */
 528         select_ldb_di_clock_source(MXC_PLL5_CLK);
 529 #endif
 530         return 0;
 531 }
 532
 533 static void set_confidx(const struct vpd_cache* vpd)
 534 {
 535         switch (vpd->product_id) {
 536         case VPD_PRODUCT_B450:
 537                 confidx = 1;
 538                 break;
 539         case VPD_PRODUCT_B650:
 540                 confidx = 2;
 541                 break;
 542         case VPD_PRODUCT_B850:
 543                 confidx = 3;
 544                 break;
 545         }
 546 }
 547
 548 int board_init(void)
 549 {
 550         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 551         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 552         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 553
 554         if (!read_vpd(&vpd, vpd_callback)) {
 555                 vpd.is_read = true;
 556                 set_confidx(&vpd);
 557         }
 558
 559         gpio_request(SUS_S3_OUT, "sus_s3_out");
 560         gpio_direction_output(SUS_S3_OUT, 1);
 561
 562         gpio_request(WIFI_EN, "wifi_en");
 563         gpio_direction_output(WIFI_EN, 1);
 564
 565 #if defined(CONFIG_VIDEO_IPUV3)
 566         if (is_b850v3())
 567                 setup_display_b850v3();
 568         else
 569                 setup_display_bx50v3();
 570
 571         gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
 572         gpio_direction_input(LVDS_BACKLIGHT_GP);
 573 #endif
 574
 575         /* address of boot parameters */
 576         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 577
 578         return 0;
 579 }
 580
 581 #ifdef CONFIG_CMD_BMODE
 582 static const struct boot_mode board_boot_modes[] = {
 583         /* 4 bit bus width */
 584         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 585         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 586         {NULL,   0},
 587 };
 588 #endif
 589
 590 void pmic_init(void)
 591 {
 592 #define I2C_PMIC                0x2
 593 #define DA9063_I2C_ADDR         0x58
 594 #define DA9063_REG_BCORE2_CFG   0x9D
 595 #define DA9063_REG_BCORE1_CFG   0x9E
 596 #define DA9063_REG_BPRO_CFG     0x9F
 597 #define DA9063_REG_BIO_CFG      0xA0
 598 #define DA9063_REG_BMEM_CFG     0xA1
 599 #define DA9063_REG_BPERI_CFG    0xA2
 600 #define DA9063_BUCK_MODE_MASK   0xC0
 601 #define DA9063_BUCK_MODE_MANUAL 0x00
 602 #define DA9063_BUCK_MODE_SLEEP  0x40
 603 #define DA9063_BUCK_MODE_SYNC   0x80
 604 #define DA9063_BUCK_MODE_AUTO   0xC0
 605
 606         uchar val;
 607
 608         i2c_set_bus_num(I2C_PMIC);
 609
 610         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 611         val &= ~DA9063_BUCK_MODE_MASK;
 612         val |= DA9063_BUCK_MODE_SYNC;
 613         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 614
 615         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 616         val &= ~DA9063_BUCK_MODE_MASK;
 617         val |= DA9063_BUCK_MODE_SYNC;
 618         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 619
 620         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 621         val &= ~DA9063_BUCK_MODE_MASK;
 622         val |= DA9063_BUCK_MODE_SYNC;
 623         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 624
 625         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 626         val &= ~DA9063_BUCK_MODE_MASK;
 627         val |= DA9063_BUCK_MODE_SYNC;
 628         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 629
 630         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 631         val &= ~DA9063_BUCK_MODE_MASK;
 632         val |= DA9063_BUCK_MODE_SYNC;
 633         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 634
 635         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 636         val &= ~DA9063_BUCK_MODE_MASK;
 637         val |= DA9063_BUCK_MODE_SYNC;
 638         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 639 }
 640
 641 int board_late_init(void)
 642 {
 643         process_vpd(&vpd);
 644
 645 #ifdef CONFIG_CMD_BMODE
 646         add_board_boot_modes(board_boot_modes);
 647 #endif
 648
 649         if (is_b850v3())
 650                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 651         else
 652                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 653
 654         /* board specific pmic init */
 655         pmic_init();
 656
 657         check_time();
 658
 659         return 0;
 660 }
 661
 662 /*
 663  * Removes the 'eth[0-9]*addr' environment variable with the given index
 664  *
 665  * @param index [in] the index of the eth_device whose variable is to be removed
 666  */
 667 static void remove_ethaddr_env_var(int index)
 668 {
 669         char env_var_name[9];
 670
 671         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 672         env_set(env_var_name, NULL);
 673 }
 674
 675 int last_stage_init(void)
 676 {
 677         int i;
 678
 679         /*
 680          * Remove first three ethaddr which may have been created by
 681          * function process_vpd().
 682          */
 683         for (i = 0; i < 3; ++i)
 684                 remove_ethaddr_env_var(i);
 685
 686         return 0;
 687 }
 688
 689 int checkboard(void)
 690 {
 691         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 692         return 0;
 693 }
 694
 695 #ifdef CONFIG_OF_BOARD_SETUP
 696 int ft_board_setup(void *blob, bd_t *bd)
 697 {
 698         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 699                                             strlen(version_string) + 1);
 700         return 0;
 701 }
 702 #endif
 703
 704 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 705 {
 706 #ifdef CONFIG_VIDEO_IPUV3
 707         /* We need at least 200ms between power on and backlight on
 708          * as per specifications from CHI MEI */
 709         mdelay(250);
 710
 711         /* enable backlight PWM 1 */
 712         pwm_init(0, 0, 0);
 713
 714         /* duty cycle 5000000ns, period: 5000000ns */
 715         pwm_config(0, 5000000, 5000000);
 716
 717         /* Backlight Power */
 718         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 719
 720         pwm_enable(0);
 721 #endif
 722
 723         return 0;
 724 }
 725
 726 U_BOOT_CMD(
 727        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 728        "enable Bx50 backlight",
 729        ""
 730 );