board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <image.h>
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <env.h>
  15 #include <linux/errno.h>
  16 #include <linux/libfdt.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <miiphy.h>
  24 #include <net.h>
  25 #include <netdev.h>
  26 #include <asm/arch/mxc_hdmi.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <power/regulator.h>
  31 #include <power/da9063_pmic.h>
  32 #include <input.h>
  33 #include <pwm.h>
  34 #include <version.h>
  35 #include <stdlib.h>
  36 #include <dm/root.h>
  37 #include "../common/ge_common.h"
  38 #include "../common/vpd_reader.h"
  39 #include "../../../drivers/net/e1000.h"
  40 #include <pci.h>
  41 #include <panel.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 static int confidx;  /* Default to generic. */
  46 static struct vpd_cache vpd;
  47
  48 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  50         PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  53         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  54
  55 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  56         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  57
  58 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  59         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  60
  61 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  62         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  63         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  64
  65 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  66
  67 int dram_init(void)
  68 {
  69         gd->ram_size = imx_ddr_size();
  70
  71         return 0;
  72 }
  73
  74 static int mx6_rgmii_rework(struct phy_device *phydev)
  75 {
  76         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  77         /* set device address 0x7 */
  78         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  79         /* offset 0x8016: CLK_25M Clock Select */
  80         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  81         /* enable register write, no post increment, address 0x7 */
  82         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  83         /* set to 125 MHz from local PLL source */
  84         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  85
  86         /* rgmii tx clock delay enable */
  87         /* set debug port address: SerDes Test and System Mode Control */
  88         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  89         /* enable rgmii tx clock delay */
  90         /* set the reserved bits to avoid board specific voltage peak issue*/
  91         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  92
  93         return 0;
  94 }
  95
  96 int board_phy_config(struct phy_device *phydev)
  97 {
  98         mx6_rgmii_rework(phydev);
  99
 100         if (phydev->drv->config)
 101                 phydev->drv->config(phydev);
 102
 103         return 0;
 104 }
 105
 106 #if defined(CONFIG_VIDEO_IPUV3)
 107 static void do_enable_backlight(struct display_info_t const *dev)
 108 {
 109         struct udevice *panel;
 110         int ret;
 111
 112         ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
 113         if (ret) {
 114                 printf("Could not find panel: %d\n", ret);
 115                 return;
 116         }
 117
 118         panel_set_backlight(panel, 100);
 119         panel_enable_backlight(panel);
 120 }
 121
 122 static void do_enable_hdmi(struct display_info_t const *dev)
 123 {
 124         imx_enable_hdmi_phy();
 125 }
 126
 127 static int is_b850v3(void)
 128 {
 129         return confidx == 3;
 130 }
 131
 132 static int detect_lcd(struct display_info_t const *dev)
 133 {
 134         return !is_b850v3();
 135 }
 136
 137 struct display_info_t const displays[] = {{
 138         .bus    = -1,
 139         .addr   = -1,
 140         .pixfmt = IPU_PIX_FMT_RGB24,
 141         .detect = detect_lcd,
 142         .enable = do_enable_backlight,
 143         .mode   = {
 144                 .name           = "G121X1-L03",
 145                 .refresh        = 60,
 146                 .xres           = 1024,
 147                 .yres           = 768,
 148                 .pixclock       = 15385,
 149                 .left_margin    = 20,
 150                 .right_margin   = 300,
 151                 .upper_margin   = 30,
 152                 .lower_margin   = 8,
 153                 .hsync_len      = 1,
 154                 .vsync_len      = 1,
 155                 .sync           = FB_SYNC_EXT,
 156                 .vmode          = FB_VMODE_NONINTERLACED
 157 } }, {
 158         .bus    = -1,
 159         .addr   = 3,
 160         .pixfmt = IPU_PIX_FMT_RGB24,
 161         .detect = detect_hdmi,
 162         .enable = do_enable_hdmi,
 163         .mode   = {
 164                 .name           = "HDMI",
 165                 .refresh        = 60,
 166                 .xres           = 1024,
 167                 .yres           = 768,
 168                 .pixclock       = 15385,
 169                 .left_margin    = 220,
 170                 .right_margin   = 40,
 171                 .upper_margin   = 21,
 172                 .lower_margin   = 7,
 173                 .hsync_len      = 60,
 174                 .vsync_len      = 10,
 175                 .sync           = FB_SYNC_EXT,
 176                 .vmode          = FB_VMODE_NONINTERLACED
 177 } } };
 178 size_t display_count = ARRAY_SIZE(displays);
 179
 180 static void enable_videopll(void)
 181 {
 182         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 183         s32 timeout = 100000;
 184
 185         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 186
 187         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 188          *   |
 189          * PLL5
 190          *   |
 191          * CS2CDR[LDB_DI0_CLK_SEL]
 192          *   |
 193          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 194          *   |
 195          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 196          */
 197
 198         clrsetbits_le32(&ccm->analog_pll_video,
 199                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 200                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 201                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 202                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 203
 204         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 205         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 206
 207         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 208
 209         while (timeout--)
 210                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 211                         break;
 212
 213         if (timeout < 0)
 214                 printf("Warning: video pll lock timeout!\n");
 215
 216         clrsetbits_le32(&ccm->analog_pll_video,
 217                         BM_ANADIG_PLL_VIDEO_BYPASS,
 218                         BM_ANADIG_PLL_VIDEO_ENABLE);
 219 }
 220
 221 static void setup_display_b850v3(void)
 222 {
 223         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 224         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 225
 226         enable_videopll();
 227
 228         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 229         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 230
 231         imx_setup_hdmi();
 232
 233         /* Set LDB_DI0 as clock source for IPU_DI0 */
 234         clrsetbits_le32(&mxc_ccm->chsccdr,
 235                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 236                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 237                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 238
 239         /* Turn on IPU LDB DI0 clocks */
 240         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 241
 242         enable_ipu_clock();
 243
 244         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 245                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 246                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 247                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 248                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 249                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 250                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 251                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 252                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 253                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 254                &iomux->gpr[2]);
 255
 256         clrbits_le32(&iomux->gpr[3],
 257                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 258                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 259                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 260 }
 261
 262 static void setup_display_bx50v3(void)
 263 {
 264         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 265         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 266
 267         enable_videopll();
 268
 269         /* When a reset/reboot is performed the display power needs to be turned
 270          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 271          * an additional 200ms here. Unfortunately we use external PMIC for
 272          * doing the reset, so can not differentiate between POR vs soft reset
 273          */
 274         mdelay(200);
 275
 276         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 277         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 278
 279         /* Set LDB_DI0 as clock source for IPU_DI0 */
 280         clrsetbits_le32(&mxc_ccm->chsccdr,
 281                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 282                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 283                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 284
 285         /* Turn on IPU LDB DI0 clocks */
 286         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 287
 288         enable_ipu_clock();
 289
 290         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 291                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 292                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 293                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 294                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 295                &iomux->gpr[2]);
 296
 297         clrsetbits_le32(&iomux->gpr[3],
 298                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 299                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 300                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 301 }
 302 #endif /* CONFIG_VIDEO_IPUV3 */
 303
 304 /*
 305  * Do not overwrite the console
 306  * Use always serial for U-Boot console
 307  */
 308 int overwrite_console(void)
 309 {
 310         return 1;
 311 }
 312
 313 #define VPD_TYPE_INVALID 0x00
 314 #define VPD_BLOCK_NETWORK 0x20
 315 #define VPD_BLOCK_HWID 0x44
 316 #define VPD_PRODUCT_B850 1
 317 #define VPD_PRODUCT_B650 2
 318 #define VPD_PRODUCT_B450 3
 319 #define VPD_HAS_MAC1 0x1
 320 #define VPD_HAS_MAC2 0x2
 321 #define VPD_MAC_ADDRESS_LENGTH 6
 322
 323 struct vpd_cache {
 324         bool is_read;
 325         u8 product_id;
 326         u8 has;
 327         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 328         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 329 };
 330
 331 /*
 332  * Extracts MAC and product information from the VPD.
 333  */
 334 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 335                         size_t size, u8 const *data)
 336 {
 337         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 338             size >= 1) {
 339                 vpd->product_id = data[0];
 340         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 341                    type != VPD_TYPE_INVALID) {
 342                 if (size >= 6) {
 343                         vpd->has |= VPD_HAS_MAC1;
 344                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 345                 }
 346                 if (size >= 12) {
 347                         vpd->has |= VPD_HAS_MAC2;
 348                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 349                 }
 350         }
 351
 352         return 0;
 353 }
 354
 355 static void process_vpd(struct vpd_cache *vpd)
 356 {
 357         int fec_index = 0;
 358         int i210_index = -1;
 359
 360         if (!vpd->is_read) {
 361                 printf("VPD wasn't read");
 362                 return;
 363         }
 364
 365         if (vpd->has & VPD_HAS_MAC1)
 366                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 367
 368         env_set("ethact", "eth0");
 369
 370         switch (vpd->product_id) {
 371         case VPD_PRODUCT_B450:
 372                 env_set("confidx", "1");
 373                 i210_index = 1;
 374                 break;
 375         case VPD_PRODUCT_B650:
 376                 env_set("confidx", "2");
 377                 i210_index = 1;
 378                 break;
 379         case VPD_PRODUCT_B850:
 380                 env_set("confidx", "3");
 381                 i210_index = 2;
 382                 break;
 383         }
 384
 385         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 386                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 387 }
 388
 389 static iomux_v3_cfg_t const misc_pads[] = {
 390         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 391         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 392         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 393         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 394         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 395         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 396         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 397         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 398 };
 399 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 400 #define WIFI_EN IMX_GPIO_NR(6, 14)
 401
 402 int board_early_init_f(void)
 403 {
 404         imx_iomux_v3_setup_multiple_pads(misc_pads,
 405                                          ARRAY_SIZE(misc_pads));
 406
 407 #if defined(CONFIG_VIDEO_IPUV3)
 408         /* Set LDB clock to Video PLL */
 409         select_ldb_di_clock_source(MXC_PLL5_CLK);
 410 #endif
 411         return 0;
 412 }
 413
 414 static void set_confidx(const struct vpd_cache* vpd)
 415 {
 416         switch (vpd->product_id) {
 417         case VPD_PRODUCT_B450:
 418                 confidx = 1;
 419                 break;
 420         case VPD_PRODUCT_B650:
 421                 confidx = 2;
 422                 break;
 423         case VPD_PRODUCT_B850:
 424                 confidx = 3;
 425                 break;
 426         }
 427 }
 428
 429 int board_init(void)
 430 {
 431         if (!read_vpd(&vpd, vpd_callback)) {
 432                 int ret, rescan;
 433
 434                 vpd.is_read = true;
 435                 set_confidx(&vpd);
 436
 437                 ret = fdtdec_resetup(&rescan);
 438                 if (!ret && rescan) {
 439                         dm_uninit();
 440                         dm_init_and_scan(false);
 441                 }
 442         }
 443
 444         gpio_request(SUS_S3_OUT, "sus_s3_out");
 445         gpio_direction_output(SUS_S3_OUT, 1);
 446
 447         gpio_request(WIFI_EN, "wifi_en");
 448         gpio_direction_output(WIFI_EN, 1);
 449
 450 #if defined(CONFIG_VIDEO_IPUV3)
 451         if (is_b850v3())
 452                 setup_display_b850v3();
 453         else
 454                 setup_display_bx50v3();
 455 #endif
 456
 457         /* address of boot parameters */
 458         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 459
 460         return 0;
 461 }
 462
 463 #ifdef CONFIG_CMD_BMODE
 464 static const struct boot_mode board_boot_modes[] = {
 465         /* 4 bit bus width */
 466         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 467         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 468         {NULL,   0},
 469 };
 470 #endif
 471
 472 void pmic_init(void)
 473 {
 474         struct udevice *reg;
 475         int ret, i;
 476         static const char * const bucks[] = {
 477                 "bcore1",
 478                 "bcore2",
 479                 "bpro",
 480                 "bmem",
 481                 "bio",
 482                 "bperi",
 483         };
 484
 485         for (i = 0; i < ARRAY_SIZE(bucks); i++) {
 486                 ret = regulator_get_by_devname(bucks[i], &reg);
 487                 if (reg < 0) {
 488                         printf("%s(): Unable to get regulator %s: %d\n",
 489                                __func__, bucks[i], ret);
 490                         continue;
 491                 }
 492                 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
 493         }
 494 }
 495
 496 int board_late_init(void)
 497 {
 498         process_vpd(&vpd);
 499
 500 #ifdef CONFIG_CMD_BMODE
 501         add_board_boot_modes(board_boot_modes);
 502 #endif
 503
 504         if (is_b850v3())
 505                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 506         else
 507                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 508
 509         /* board specific pmic init */
 510         pmic_init();
 511
 512         check_time();
 513
 514         pci_init();
 515
 516         return 0;
 517 }
 518
 519 /*
 520  * Removes the 'eth[0-9]*addr' environment variable with the given index
 521  *
 522  * @param index [in] the index of the eth_device whose variable is to be removed
 523  */
 524 static void remove_ethaddr_env_var(int index)
 525 {
 526         char env_var_name[9];
 527
 528         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 529         env_set(env_var_name, NULL);
 530 }
 531
 532 int last_stage_init(void)
 533 {
 534         int i;
 535
 536         /*
 537          * Remove first three ethaddr which may have been created by
 538          * function process_vpd().
 539          */
 540         for (i = 0; i < 3; ++i)
 541                 remove_ethaddr_env_var(i);
 542
 543         return 0;
 544 }
 545
 546 int checkboard(void)
 547 {
 548         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 549         return 0;
 550 }
 551
 552 #ifdef CONFIG_OF_BOARD_SETUP
 553 int ft_board_setup(void *blob, bd_t *bd)
 554 {
 555         char *rtc_status = env_get("rtc_status");
 556
 557         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 558                     strlen(version_string) + 1);
 559
 560         fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
 561                     strlen(rtc_status) + 1);
 562         return 0;
 563 }
 564 #endif
 565
 566 int board_fit_config_name_match(const char *name)
 567 {
 568         if (!vpd.is_read)
 569                 return strcmp(name, "imx6q-bx50v3");
 570
 571         switch (vpd.product_id) {
 572         case VPD_PRODUCT_B450:
 573                 return strcmp(name, "imx6q-b450v3");
 574         case VPD_PRODUCT_B650:
 575                 return strcmp(name, "imx6q-b650v3");
 576         case VPD_PRODUCT_B850:
 577                 return strcmp(name, "imx6q-b850v3");
 578         default:
 579                 return -1;
 580         }
 581 }
 582
 583 int embedded_dtb_select(void)
 584 {
 585         vpd.is_read = false;
 586         return fdtdec_setup();
 587 }