board/gdsys/mpc8308/mpc8308.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <init.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/global_data.h>
  13
  14 #include "mpc8308.h"
  15 #include <gdsys_fpga.h>
  16
  17 #define REFLECTION_TESTPATTERN 0xdede
  18 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  19
  20 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  21 #define REFLECTION_TESTREG reflection_low
  22 #else
  23 #define REFLECTION_TESTREG reflection_high
  24 #endif
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
  29 /* as gpio output status cannot be read back, we have to buffer it locally */
  30 u32 gpio0_out;
  31
  32 void setbits_gpio0_out(u32 mask)
  33 {
  34         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  35
  36         gpio0_out |= mask;
  37         out_be32(&immr->gpio[0].dat, gpio0_out);
  38 }
  39
  40 void clrbits_gpio0_out(u32 mask)
  41 {
  42         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  43
  44         gpio0_out &= ~mask;
  45         out_be32(&immr->gpio[0].dat, gpio0_out);
  46 }
  47
  48 int get_fpga_state(uint dev)
  49 {
  50         return gd->arch.fpga_state[dev];
  51 }
  52
  53 int board_early_init_f(void)
  54 {
  55         uint k;
  56
  57         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  58                 gd->arch.fpga_state[k] = 0;
  59
  60         return 0;
  61 }
  62
  63 int board_early_init_r(void)
  64 {
  65         uint k;
  66         uint ctr;
  67
  68         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  69                 gd->arch.fpga_state[k] = 0;
  70
  71         /*
  72          * reset FPGA
  73          */
  74         mpc8308_init();
  75
  76         mpc8308_set_fpga_reset(1);
  77
  78         mpc8308_setup_hw();
  79
  80         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  81                 ctr = 0;
  82                 while (!mpc8308_get_fpga_done(k)) {
  83                         mdelay(100);
  84                         if (ctr++ > 5) {
  85                                 gd->arch.fpga_state[k] |=
  86                                         FPGA_STATE_DONE_FAILED;
  87                                 break;
  88                         }
  89                 }
  90         }
  91
  92         udelay(10);
  93
  94         mpc8308_set_fpga_reset(0);
  95
  96         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  97                 /*
  98                  * wait for fpga out of reset
  99                  */
 100                 ctr = 0;
 101                 while (1) {
 102                         u16 val;
 103
 104                         FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
 105
 106                         FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
 107                         if (val == REFLECTION_TESTPATTERN_INV)
 108                                 break;
 109
 110                         mdelay(100);
 111                         if (ctr++ > 5) {
 112                                 gd->arch.fpga_state[k] |=
 113                                         FPGA_STATE_REFLECTION_FAILED;
 114                                 break;
 115                         }
 116                 }
 117         }
 118
 119         return 0;
 120 }
 121 #endif