board/gdsys/a38x/hydra.c

   1 #include <common.h>
   2 #include <command.h>
   3 #include <console.h> /* ctrlc */
   4 #include <asm/io.h>
   5
   6 #include "hydra.h"
   7
   8 enum {
   9         HWVER_100 = 0,
  10         HWVER_110 = 1,
  11         HWVER_120 = 2,
  12 };
  13
  14 static struct pci_device_id hydra_supported[] = {
  15         { 0x6d5e, 0xcdc1 },
  16         {}
  17 };
  18
  19 static struct ihs_fpga *fpga;
  20
  21 struct ihs_fpga *get_fpga(void)
  22 {
  23         return fpga;
  24 }
  25
  26 void print_hydra_version(uint index)
  27 {
  28         u32 versions = readl(&fpga->versions);
  29         u32 fpga_version = readl(&fpga->fpga_version);
  30
  31         uint hardware_version = versions & 0xf;
  32
  33         printf("FPGA%u: mapped to %p\n       ", index, fpga);
  34
  35         switch (hardware_version) {
  36         case HWVER_100:
  37                 printf("HW-Ver 1.00\n");
  38                 break;
  39
  40         case HWVER_110:
  41                 printf("HW-Ver 1.10\n");
  42                 break;
  43
  44         case HWVER_120:
  45                 printf("HW-Ver 1.20\n");
  46                 break;
  47
  48         default:
  49                 printf("HW-Ver %d(not supported)\n",
  50                        hardware_version);
  51                 break;
  52         }
  53
  54         printf("       FPGA V %d.%02d\n",
  55                fpga_version / 100, fpga_version % 100);
  56 }
  57
  58 void hydra_initialize(void)
  59 {
  60         uint i;
  61         pci_dev_t devno;
  62
  63         /* Find and probe all the matching PCI devices */
  64         for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
  65                 u32 val;
  66
  67                 /* Try to enable I/O accesses and bus-mastering */
  68                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  69                 pci_write_config_dword(devno, PCI_COMMAND, val);
  70
  71                 /* Make sure it worked */
  72                 pci_read_config_dword(devno, PCI_COMMAND, &val);
  73                 if (!(val & PCI_COMMAND_MEMORY)) {
  74                         puts("Can't enable I/O memory\n");
  75                         continue;
  76                 }
  77                 if (!(val & PCI_COMMAND_MASTER)) {
  78                         puts("Can't enable bus-mastering\n");
  79                         continue;
  80                 }
  81
  82                 /* read FPGA details */
  83                 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  84                                    PCI_REGION_MEM);
  85
  86                 print_hydra_version(i);
  87         }
  88 }
  89
  90 #define REFL_PATTERN (0xdededede)
  91 #define REFL_PATTERN_INV (~REFL_PATTERN)
  92
  93 int do_hydrate(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  94 {
  95         uint k = 0;
  96         void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE +
  97                                                     0x4000);
  98
  99         if (!fpga)
 100                 return -1;
 101
 102         while (1) {
 103                 u32 res;
 104
 105                 writel(REFL_PATTERN, &fpga->reflection_low);
 106                 res = readl(&fpga->reflection_low);
 107                 if (res != REFL_PATTERN_INV)
 108                         printf("round %u: read %08x, expected %08x\n",
 109                                k, res, REFL_PATTERN_INV);
 110                 writel(REFL_PATTERN_INV, &fpga->reflection_low);
 111                 res = readl(&fpga->reflection_low);
 112                 if (res != REFL_PATTERN)
 113                         printf("round %u: read %08x, expected %08x\n",
 114                                k, res, REFL_PATTERN);
 115
 116                 res = readl(pcie2_base + 0x118) & 0x1f;
 117                 if (res)
 118                         printf("FrstErrPtr %u\n", res);
 119                 res = readl(pcie2_base + 0x104);
 120                 if (res) {
 121                         printf("Uncorrectable Error Status 0x%08x\n", res);
 122                         writel(res, pcie2_base + 0x104);
 123                 }
 124
 125                 if (!(++k % 10000))
 126                         printf("round %u\n", k);
 127
 128                 if (ctrlc())
 129                         break;
 130         }
 131
 132         return 0;
 133 }
 134
 135 U_BOOT_CMD(
 136         hydrate,        1,      0,      do_hydrate,
 137         "hydra reflection test",
 138         "hydra reflection test"
 139 );