board/gateworks/gw_ventana/gw_ventana_spl.c

   1 /*
   2  * Copyright (C) 2014 Gateworks Corporation
   3  * Author: Tim Harvey <tharvey@gateworks.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/mx6-ddr.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/mxc_i2c.h>
  17 #include <environment.h>
  18 #include <i2c.h>
  19 #include <spl.h>
  20
  21 #include "gsc.h"
  22 #include "common.h"
  23
  24 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  25 #define GSC_EEPROM_DDR_SIZE     0x2B    /* enum (512,1024,2048) MB */
  26 #define GSC_EEPROM_DDR_WIDTH    0x2D    /* enum (32,64) bit */
  27
  28 /* configure MX6Q/DUAL mmdc DDR io registers */
  29 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  30         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  31         .dram_sdclk_0 = 0x00020030,
  32         .dram_sdclk_1 = 0x00020030,
  33         .dram_cas = 0x00020030,
  34         .dram_ras = 0x00020030,
  35         .dram_reset = 0x00020030,
  36         /* SDCKE[0:1]: 100k pull-up */
  37         .dram_sdcke0 = 0x00003000,
  38         .dram_sdcke1 = 0x00003000,
  39         /* SDBA2: pull-up disabled */
  40         .dram_sdba2 = 0x00000000,
  41         /* SDODT[0:1]: 100k pull-up, 40 ohm */
  42         .dram_sdodt0 = 0x00003030,
  43         .dram_sdodt1 = 0x00003030,
  44         /* SDQS[0:7]: Differential input, 40 ohm */
  45         .dram_sdqs0 = 0x00000030,
  46         .dram_sdqs1 = 0x00000030,
  47         .dram_sdqs2 = 0x00000030,
  48         .dram_sdqs3 = 0x00000030,
  49         .dram_sdqs4 = 0x00000030,
  50         .dram_sdqs5 = 0x00000030,
  51         .dram_sdqs6 = 0x00000030,
  52         .dram_sdqs7 = 0x00000030,
  53
  54         /* DQM[0:7]: Differential input, 40 ohm */
  55         .dram_dqm0 = 0x00020030,
  56         .dram_dqm1 = 0x00020030,
  57         .dram_dqm2 = 0x00020030,
  58         .dram_dqm3 = 0x00020030,
  59         .dram_dqm4 = 0x00020030,
  60         .dram_dqm5 = 0x00020030,
  61         .dram_dqm6 = 0x00020030,
  62         .dram_dqm7 = 0x00020030,
  63 };
  64
  65 /* configure MX6Q/DUAL mmdc GRP io registers */
  66 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  67         /* DDR3 */
  68         .grp_ddr_type = 0x000c0000,
  69         .grp_ddrmode_ctl = 0x00020000,
  70         /* disable DDR pullups */
  71         .grp_ddrpke = 0x00000000,
  72         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  73         .grp_addds = 0x00000030,
  74         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  75         .grp_ctlds = 0x00000030,
  76         /* DATA[00:63]: Differential input, 40 ohm */
  77         .grp_ddrmode = 0x00020000,
  78         .grp_b0ds = 0x00000030,
  79         .grp_b1ds = 0x00000030,
  80         .grp_b2ds = 0x00000030,
  81         .grp_b3ds = 0x00000030,
  82         .grp_b4ds = 0x00000030,
  83         .grp_b5ds = 0x00000030,
  84         .grp_b6ds = 0x00000030,
  85         .grp_b7ds = 0x00000030,
  86 };
  87
  88 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  89 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  90         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  91         .dram_sdclk_0 = 0x00020030,
  92         .dram_sdclk_1 = 0x00020030,
  93         .dram_cas = 0x00020030,
  94         .dram_ras = 0x00020030,
  95         .dram_reset = 0x00020030,
  96         /* SDCKE[0:1]: 100k pull-up */
  97         .dram_sdcke0 = 0x00003000,
  98         .dram_sdcke1 = 0x00003000,
  99         /* SDBA2: pull-up disabled */
 100         .dram_sdba2 = 0x00000000,
 101         /* SDODT[0:1]: 100k pull-up, 40 ohm */
 102         .dram_sdodt0 = 0x00003030,
 103         .dram_sdodt1 = 0x00003030,
 104         /* SDQS[0:7]: Differential input, 40 ohm */
 105         .dram_sdqs0 = 0x00000030,
 106         .dram_sdqs1 = 0x00000030,
 107         .dram_sdqs2 = 0x00000030,
 108         .dram_sdqs3 = 0x00000030,
 109         .dram_sdqs4 = 0x00000030,
 110         .dram_sdqs5 = 0x00000030,
 111         .dram_sdqs6 = 0x00000030,
 112         .dram_sdqs7 = 0x00000030,
 113
 114         /* DQM[0:7]: Differential input, 40 ohm */
 115         .dram_dqm0 = 0x00020030,
 116         .dram_dqm1 = 0x00020030,
 117         .dram_dqm2 = 0x00020030,
 118         .dram_dqm3 = 0x00020030,
 119         .dram_dqm4 = 0x00020030,
 120         .dram_dqm5 = 0x00020030,
 121         .dram_dqm6 = 0x00020030,
 122         .dram_dqm7 = 0x00020030,
 123 };
 124
 125 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 126 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 127         /* DDR3 */
 128         .grp_ddr_type = 0x000c0000,
 129         /* SDQS[0:7]: Differential input, 40 ohm */
 130         .grp_ddrmode_ctl = 0x00020000,
 131         /* disable DDR pullups */
 132         .grp_ddrpke = 0x00000000,
 133         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 134         .grp_addds = 0x00000030,
 135         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 136         .grp_ctlds = 0x00000030,
 137         /* DATA[00:63]: Differential input, 40 ohm */
 138         .grp_ddrmode = 0x00020000,
 139         .grp_b0ds = 0x00000030,
 140         .grp_b1ds = 0x00000030,
 141         .grp_b2ds = 0x00000030,
 142         .grp_b3ds = 0x00000030,
 143         .grp_b4ds = 0x00000030,
 144         .grp_b5ds = 0x00000030,
 145         .grp_b6ds = 0x00000030,
 146         .grp_b7ds = 0x00000030,
 147 };
 148
 149 /* MT41K64M16JT-125 (1Gb density) */
 150 static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
 151         .mem_speed = 1600,
 152         .density = 1,
 153         .width = 16,
 154         .banks = 8,
 155         .rowaddr = 13,
 156         .coladdr = 10,
 157         .pagesz = 2,
 158         .trcd = 1375,
 159         .trcmin = 4875,
 160         .trasmin = 3500,
 161 };
 162
 163 /* MT41K128M16JT-125 (2Gb density) */
 164 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 165         .mem_speed = 1600,
 166         .density = 2,
 167         .width = 16,
 168         .banks = 8,
 169         .rowaddr = 14,
 170         .coladdr = 10,
 171         .pagesz = 2,
 172         .trcd = 1375,
 173         .trcmin = 4875,
 174         .trasmin = 3500,
 175 };
 176
 177 /* MT41K256M16HA-125 (4Gb density) */
 178 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
 179         .mem_speed = 1600,
 180         .density = 4,
 181         .width = 16,
 182         .banks = 8,
 183         .rowaddr = 15,
 184         .coladdr = 10,
 185         .pagesz = 2,
 186         .trcd = 1375,
 187         .trcmin = 4875,
 188         .trasmin = 3500,
 189 };
 190
 191 /* MT41K512M16HA-125 (8Gb density) */
 192 static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
 193         .mem_speed = 1600,
 194         .density = 8,
 195         .width = 16,
 196         .banks = 8,
 197         .rowaddr = 16,
 198         .coladdr = 10,
 199         .pagesz = 2,
 200         .trcd = 1375,
 201         .trcmin = 4875,
 202         .trasmin = 3500,
 203 };
 204
 205 /*
 206  * calibration - these are the various CPU/DDR3 combinations we support
 207  */
 208 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
 209         /* write leveling calibration determine */
 210         .p0_mpwldectrl0 = 0x004C004E,
 211         .p0_mpwldectrl1 = 0x00440044,
 212         /* Read DQS Gating calibration */
 213         .p0_mpdgctrl0 = 0x42440247,
 214         .p0_mpdgctrl1 = 0x02310232,
 215         /* Read Calibration: DQS delay relative to DQ read access */
 216         .p0_mprddlctl = 0x45424746,
 217         /* Write Calibration: DQ/DM delay relative to DQS write access */
 218         .p0_mpwrdlctl = 0x33382C31,
 219 };
 220
 221 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
 222         /* write leveling calibration determine */
 223         .p0_mpwldectrl0 = 0x001B0016,
 224         .p0_mpwldectrl1 = 0x000C000E,
 225         /* Read DQS Gating calibration */
 226         .p0_mpdgctrl0 = 0x4324033A,
 227         .p0_mpdgctrl1 = 0x00000000,
 228         /* Read Calibration: DQS delay relative to DQ read access */
 229         .p0_mprddlctl = 0x40403438,
 230         /* Write Calibration: DQ/DM delay relative to DQS write access */
 231         .p0_mpwrdlctl = 0x40403D36,
 232 };
 233
 234 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
 235         /* write leveling calibration determine */
 236         .p0_mpwldectrl0 = 0x00420043,
 237         .p0_mpwldectrl1 = 0x0016001A,
 238         /* Read DQS Gating calibration */
 239         .p0_mpdgctrl0 = 0x4238023B,
 240         .p0_mpdgctrl1 = 0x00000000,
 241         /* Read Calibration: DQS delay relative to DQ read access */
 242         .p0_mprddlctl = 0x40404849,
 243         /* Write Calibration: DQ/DM delay relative to DQS write access */
 244         .p0_mpwrdlctl = 0x40402E2F,
 245 };
 246
 247 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
 248         /* write leveling calibration determine */
 249         .p0_mpwldectrl0 = 0x00190017,
 250         .p0_mpwldectrl1 = 0x00140026,
 251         /* Read DQS Gating calibration */
 252         .p0_mpdgctrl0 = 0x43380347,
 253         .p0_mpdgctrl1 = 0x433C034D,
 254         /* Read Calibration: DQS delay relative to DQ read access */
 255         .p0_mprddlctl = 0x3C313539,
 256         /* Write Calibration: DQ/DM delay relative to DQS write access */
 257         .p0_mpwrdlctl = 0x36393C39,
 258 };
 259
 260 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
 261         /* write leveling calibration determine */
 262         .p0_mpwldectrl0 = 0x003C003C,
 263         .p0_mpwldectrl1 = 0x001F002A,
 264         /* Read DQS Gating calibration */
 265         .p0_mpdgctrl0 = 0x42410244,
 266         .p0_mpdgctrl1 = 0x4234023A,
 267         /* Read Calibration: DQS delay relative to DQ read access */
 268         .p0_mprddlctl = 0x484A4C4B,
 269         /* Write Calibration: DQ/DM delay relative to DQS write access */
 270         .p0_mpwrdlctl = 0x33342B32,
 271 };
 272
 273 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
 274         /* write leveling calibration determine */
 275         .p0_mpwldectrl0 = 0x00190017,
 276         .p0_mpwldectrl1 = 0x00140026,
 277         .p1_mpwldectrl0 = 0x0021001C,
 278         .p1_mpwldectrl1 = 0x0011001D,
 279         /* Read DQS Gating calibration */
 280         .p0_mpdgctrl0 = 0x43380347,
 281         .p0_mpdgctrl1 = 0x433C034D,
 282         .p1_mpdgctrl0 = 0x032C0324,
 283         .p1_mpdgctrl1 = 0x03310232,
 284         /* Read Calibration: DQS delay relative to DQ read access */
 285         .p0_mprddlctl = 0x3C313539,
 286         .p1_mprddlctl = 0x37343141,
 287         /* Write Calibration: DQ/DM delay relative to DQS write access */
 288         .p0_mpwrdlctl = 0x36393C39,
 289         .p1_mpwrdlctl = 0x42344438,
 290 };
 291
 292 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
 293         /* write leveling calibration determine */
 294         .p0_mpwldectrl0 = 0x003C003C,
 295         .p0_mpwldectrl1 = 0x001F002A,
 296         .p1_mpwldectrl0 = 0x00330038,
 297         .p1_mpwldectrl1 = 0x0022003F,
 298         /* Read DQS Gating calibration */
 299         .p0_mpdgctrl0 = 0x42410244,
 300         .p0_mpdgctrl1 = 0x4234023A,
 301         .p1_mpdgctrl0 = 0x022D022D,
 302         .p1_mpdgctrl1 = 0x021C0228,
 303         /* Read Calibration: DQS delay relative to DQ read access */
 304         .p0_mprddlctl = 0x484A4C4B,
 305         .p1_mprddlctl = 0x4B4D4E4B,
 306         /* Write Calibration: DQ/DM delay relative to DQS write access */
 307         .p0_mpwrdlctl = 0x33342B32,
 308         .p1_mpwrdlctl = 0x3933332B,
 309 };
 310
 311 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
 312         /* write leveling calibration determine */
 313         .p0_mpwldectrl0 = 0x001E001A,
 314         .p0_mpwldectrl1 = 0x0026001F,
 315         /* Read DQS Gating calibration */
 316         .p0_mpdgctrl0 = 0x43370349,
 317         .p0_mpdgctrl1 = 0x032D0327,
 318         /* Read Calibration: DQS delay relative to DQ read access */
 319         .p0_mprddlctl = 0x3D303639,
 320         /* Write Calibration: DQ/DM delay relative to DQS write access */
 321         .p0_mpwrdlctl = 0x32363934,
 322 };
 323
 324 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
 325         /* write leveling calibration determine */
 326         .p0_mpwldectrl0 = 0X00480047,
 327         .p0_mpwldectrl1 = 0X003D003F,
 328         /* Read DQS Gating calibration */
 329         .p0_mpdgctrl0 = 0X423E0241,
 330         .p0_mpdgctrl1 = 0X022B022C,
 331         /* Read Calibration: DQS delay relative to DQ read access */
 332         .p0_mprddlctl = 0X49454A4A,
 333         /* Write Calibration: DQ/DM delay relative to DQS write access */
 334         .p0_mpwrdlctl = 0X2E372C32,
 335 };
 336
 337 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 338         /* write leveling calibration determine */
 339         .p0_mpwldectrl0 = 0X00220021,
 340         .p0_mpwldectrl1 = 0X00200030,
 341         .p1_mpwldectrl0 = 0X002D0027,
 342         .p1_mpwldectrl1 = 0X00150026,
 343         /* Read DQS Gating calibration */
 344         .p0_mpdgctrl0 = 0x43330342,
 345         .p0_mpdgctrl1 = 0x0339034A,
 346         .p1_mpdgctrl0 = 0x032F0325,
 347         .p1_mpdgctrl1 = 0x032F022E,
 348         /* Read Calibration: DQS delay relative to DQ read access */
 349         .p0_mprddlctl = 0X3A2E3437,
 350         .p1_mprddlctl = 0X35312F3F,
 351         /* Write Calibration: DQ/DM delay relative to DQS write access */
 352         .p0_mpwrdlctl = 0X33363B37,
 353         .p1_mpwrdlctl = 0X40304239,
 354 };
 355
 356 static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
 357         /* write leveling calibration determine */
 358         .p0_mpwldectrl0 = 0x0048004A,
 359         .p0_mpwldectrl1 = 0x003F004A,
 360         .p1_mpwldectrl0 = 0x001E0028,
 361         .p1_mpwldectrl1 = 0x002C0043,
 362         /* Read DQS Gating calibration */
 363         .p0_mpdgctrl0 = 0x02250219,
 364         .p0_mpdgctrl1 = 0x01790202,
 365         .p1_mpdgctrl0 = 0x02080208,
 366         .p1_mpdgctrl1 = 0x016C0175,
 367         /* Read Calibration: DQS delay relative to DQ read access */
 368         .p0_mprddlctl = 0x4A4C4D4C,
 369         .p1_mprddlctl = 0x494C4A48,
 370         /* Write Calibration: DQ/DM delay relative to DQS write access */
 371         .p0_mpwrdlctl = 0x403F3437,
 372         .p1_mpwrdlctl = 0x383A3930,
 373 };
 374
 375 static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
 376         /* write leveling calibration determine */
 377         .p0_mpwldectrl0 = 0x001F003F,
 378         .p0_mpwldectrl1 = 0x001F001F,
 379         .p1_mpwldectrl0 = 0x001F004E,
 380         .p1_mpwldectrl1 = 0x0059001F,
 381         /* Read DQS Gating calibration */
 382         .p0_mpdgctrl0   = 0x42220225,
 383         .p0_mpdgctrl1   = 0x0213021F,
 384         .p1_mpdgctrl0   = 0x022C0242,
 385         .p1_mpdgctrl1   = 0x022C0244,
 386         /* Read Calibration: DQS delay relative to DQ read access */
 387         .p0_mprddlctl   = 0x474A4C4A,
 388         .p1_mprddlctl   = 0x48494C45,
 389         /* Write Calibration: DQ/DM delay relative to DQS write access */
 390         .p0_mpwrdlctl   = 0x3F3F3F36,
 391         .p1_mpwrdlctl   = 0x3F36363F,
 392 };
 393
 394 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
 395         /* write leveling calibration determine */
 396         .p0_mpwldectrl0 = 0x002A0025,
 397         .p0_mpwldectrl1 = 0x003A002A,
 398         /* Read DQS Gating calibration */
 399         .p0_mpdgctrl0 = 0x43430356,
 400         .p0_mpdgctrl1 = 0x033C0335,
 401         /* Read Calibration: DQS delay relative to DQ read access */
 402         .p0_mprddlctl = 0x4B373F42,
 403         /* Write Calibration: DQ/DM delay relative to DQS write access */
 404         .p0_mpwrdlctl = 0x303E3C36,
 405 };
 406
 407 static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
 408         /* write leveling calibration determine */
 409         .p0_mpwldectrl0 = 0x00230020,
 410         .p0_mpwldectrl1 = 0x002F002A,
 411         .p1_mpwldectrl0 = 0x001D0027,
 412         .p1_mpwldectrl1 = 0x00100023,
 413         /* Read DQS Gating calibration */
 414         .p0_mpdgctrl0 = 0x03250339,
 415         .p0_mpdgctrl1 = 0x031C0316,
 416         .p1_mpdgctrl0 = 0x03210331,
 417         .p1_mpdgctrl1 = 0x031C025A,
 418         /* Read Calibration: DQS delay relative to DQ read access */
 419         .p0_mprddlctl = 0x40373C40,
 420         .p1_mprddlctl = 0x3A373646,
 421         /* Write Calibration: DQ/DM delay relative to DQS write access */
 422         .p0_mpwrdlctl = 0x2E353933,
 423         .p1_mpwrdlctl = 0x3C2F3F35,
 424 };
 425
 426 static void spl_dram_init(int width, int size_mb, int board_model)
 427 {
 428         struct mx6_ddr3_cfg *mem = NULL;
 429         struct mx6_mmdc_calibration *calib = NULL;
 430         struct mx6_ddr_sysinfo sysinfo = {
 431                 /* width of data bus:0=16,1=32,2=64 */
 432                 .dsize = width/32,
 433                 /* config for full 4GB range so that get_mem_size() works */
 434                 .cs_density = 32, /* 32Gb per CS */
 435                 /* single chip select */
 436                 .ncs = 1,
 437                 .cs1_mirror = 0,
 438                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 439 #ifdef RTT_NOM_120OHM
 440                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 441 #else
 442                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 443 #endif
 444                 .walat = 1,     /* Write additional latency */
 445                 .ralat = 5,     /* Read additional latency */
 446                 .mif3_mode = 3, /* Command prediction working mode */
 447                 .bi_on = 1,     /* Bank interleaving enabled */
 448                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 449                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 450                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 451                 .ddr_type = DDR_TYPE_DDR3,
 452                 .refsel = 1,    /* Refresh cycles at 32KHz */
 453                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 454         };
 455
 456         /*
 457          * MMDC Calibration requires the following data:
 458          *   mx6_mmdc_calibration - board-specific calibration (routing delays)
 459          *      these calibration values depend on board routing, SoC, and DDR
 460          *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
 461          *   mx6_ddr_cfg - chip specific timing/layout details
 462          */
 463         if (width == 16 && size_mb == 128) {
 464                 mem = &mt41k64m16jt_125;
 465                 if (is_cpu_type(MXC_CPU_MX6Q))
 466                         ;
 467                 else
 468                         calib = &mx6sdl_64x16_mmdc_calib;
 469                 debug("1gB density\n");
 470         } else if (width == 16 && size_mb == 256) {
 471                 /* 1x 2Gb density chip - same calib as 2x 2Gb */
 472                 mem = &mt41k128m16jt_125;
 473                 if (is_cpu_type(MXC_CPU_MX6Q))
 474                         calib = &mx6dq_128x32_mmdc_calib;
 475                 else
 476                         calib = &mx6sdl_128x32_mmdc_calib;
 477                 debug("2gB density\n");
 478         } else if (width == 16 && size_mb == 512) {
 479                 mem = &mt41k256m16ha_125;
 480                 if (is_cpu_type(MXC_CPU_MX6Q))
 481                         calib = &mx6dq_256x16_mmdc_calib;
 482                 else
 483                         calib = &mx6sdl_256x16_mmdc_calib;
 484                 debug("4gB density\n");
 485         } else if (width == 32 && size_mb == 256) {
 486                 /* Same calib as width==16, size==128 */
 487                 mem = &mt41k64m16jt_125;
 488                 if (is_cpu_type(MXC_CPU_MX6Q))
 489                         ;
 490                 else
 491                         calib = &mx6sdl_64x16_mmdc_calib;
 492                 debug("1gB density\n");
 493         } else if (width == 32 && size_mb == 512) {
 494                 mem = &mt41k128m16jt_125;
 495                 if (is_cpu_type(MXC_CPU_MX6Q))
 496                         calib = &mx6dq_128x32_mmdc_calib;
 497                 else
 498                         calib = &mx6sdl_128x32_mmdc_calib;
 499                 debug("2gB density\n");
 500         }  else if (width == 32 && size_mb == 1024) {
 501                 mem = &mt41k256m16ha_125;
 502                 if (is_cpu_type(MXC_CPU_MX6Q))
 503                         calib = &mx6dq_256x32_mmdc_calib;
 504                 else
 505                         calib = &mx6sdl_256x32_mmdc_calib;
 506                 debug("4gB density\n");
 507         } else if (width == 32 && size_mb == 2048) {
 508                 mem = &mt41k512m16ha_125;
 509                 if (is_cpu_type(MXC_CPU_MX6Q))
 510                         calib = &mx6dq_512x32_mmdc_calib;
 511                 debug("8gB density\n");
 512         } else if (width == 64 && size_mb == 512) {
 513                 mem = &mt41k64m16jt_125;
 514                 debug("1gB density\n");
 515         } else if (width == 64 && size_mb == 1024) {
 516                 mem = &mt41k128m16jt_125;
 517                 if (is_cpu_type(MXC_CPU_MX6Q))
 518                         calib = &mx6dq_128x64_mmdc_calib;
 519                 else
 520                         calib = &mx6sdl_128x64_mmdc_calib;
 521                 debug("2gB density\n");
 522         } else if (width == 64 && size_mb == 2048) {
 523                 mem = &mt41k256m16ha_125;
 524                 if (is_cpu_type(MXC_CPU_MX6Q))
 525                         calib = &mx6dq_256x64_mmdc_calib;
 526                 else
 527                         calib = &mx6sdl_256x64_mmdc_calib;
 528                 debug("4gB density\n");
 529         } else if (width == 64 && size_mb == 4096) {
 530                 switch(board_model) {
 531                 case GW5903:
 532                         /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
 533                         mem = &mt41k256m16ha_125;
 534                         debug("4gB density\n");
 535                         if (!is_cpu_type(MXC_CPU_MX6Q)) {
 536                                 calib = &mx6sdl_256x64x2_mmdc_calib;
 537                                 sysinfo.ncs = 2;
 538                                 sysinfo.cs_density = 18; /* CS0_END=71 */
 539                                 sysinfo.cs1_mirror = 1; /* mirror enabled */
 540                         }
 541                         break;
 542                 default:
 543                         mem = &mt41k512m16ha_125;
 544                         if (is_cpu_type(MXC_CPU_MX6Q))
 545                                 calib = &mx6dq_512x64_mmdc_calib;
 546                         debug("8gB density\n");
 547                         break;
 548                 }
 549         }
 550
 551         if (!(mem && calib)) {
 552                 puts("Error: Invalid Calibration/Board Configuration\n");
 553                 printf("MEM    : %s\n", mem ? "OKAY" : "NULL");
 554                 printf("CALIB  : %s\n", calib ? "OKAY" : "NULL");
 555                 printf("CPUTYPE: %s\n",
 556                        is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
 557                 printf("SIZE_MB: %d\n", size_mb);
 558                 printf("WIDTH  : %d\n", width);
 559                 hang();
 560         }
 561
 562         if (is_cpu_type(MXC_CPU_MX6Q))
 563                 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
 564                                  &mx6dq_grp_ioregs);
 565         else
 566                 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
 567                                   &mx6sdl_grp_ioregs);
 568         mx6_dram_cfg(&sysinfo, calib, mem);
 569 }
 570
 571 static void ccgr_init(void)
 572 {
 573         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 574
 575         writel(0x00C03F3F, &ccm->CCGR0);
 576         writel(0x0030FC03, &ccm->CCGR1);
 577         writel(0x0FFFC000, &ccm->CCGR2);
 578         writel(0x3FF00000, &ccm->CCGR3);
 579         writel(0xFFFFF300, &ccm->CCGR4);        /* enable NAND/GPMI/BCH clks */
 580         writel(0x0F0000C3, &ccm->CCGR5);
 581         writel(0x000003FF, &ccm->CCGR6);
 582 }
 583
 584 /*
 585  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 586  * - we have a stack and a place to store GD, both in SRAM
 587  * - no variable global data is available
 588  */
 589 void board_init_f(ulong dummy)
 590 {
 591         struct ventana_board_info ventana_info;
 592         int board_model;
 593
 594         /* setup clock gating */
 595         ccgr_init();
 596
 597         /* setup AIPS and disable watchdog */
 598         arch_cpu_init();
 599
 600         /* setup AXI */
 601         gpr_init();
 602
 603         /* iomux and setup of i2c */
 604         setup_iomux_uart();
 605         setup_ventana_i2c();
 606
 607         /* setup GP timer */
 608         timer_init();
 609
 610         /* UART clocks enabled and gd valid - init serial console */
 611         preloader_console_init();
 612
 613         /* read/validate EEPROM info to determine board model and SDRAM cfg */
 614         board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 615
 616         /* configure model-specific gpio */
 617         setup_iomux_gpio(board_model, &ventana_info);
 618
 619         /* provide some some default: 32bit 128MB */
 620         if (GW_UNKNOWN == board_model)
 621                 hang();
 622
 623         /* configure MMDC for SDRAM width/size and per-model calibration */
 624         spl_dram_init(8 << ventana_info.sdram_width,
 625                       16 << ventana_info.sdram_size,
 626                       board_model);
 627 }
 628
 629 void board_boot_order(u32 *spl_boot_list)
 630 {
 631         spl_boot_list[0] = spl_boot_device();
 632         switch (spl_boot_list[0]) {
 633         case BOOT_DEVICE_NAND:
 634                 spl_boot_list[1] = BOOT_DEVICE_MMC1;
 635                 spl_boot_list[2] = BOOT_DEVICE_UART;
 636                 break;
 637         case BOOT_DEVICE_MMC1:
 638                 spl_boot_list[1] = BOOT_DEVICE_UART;
 639                 break;
 640         }
 641 }
 642
 643 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
 644 /* its our chance to print info about boot device */
 645 void spl_board_init(void)
 646 {
 647         /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
 648         u32 boot_device = spl_boot_device();
 649
 650         switch (boot_device) {
 651         case BOOT_DEVICE_MMC1:
 652                 puts("Booting from MMC\n");
 653                 break;
 654         case BOOT_DEVICE_NAND:
 655                 puts("Booting from NAND\n");
 656                 break;
 657         case BOOT_DEVICE_SATA:
 658                 puts("Booting from SATA\n");
 659                 break;
 660         default:
 661                 puts("Unknown boot device\n");
 662         }
 663
 664         /* PMIC init */
 665         setup_pmic();
 666 }
 667
 668 #ifdef CONFIG_SPL_OS_BOOT
 669 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
 670 int spl_start_uboot(void)
 671 {
 672         unsigned char ret = 1;
 673
 674         debug("%s\n", __func__);
 675 #ifdef CONFIG_SPL_ENV_SUPPORT
 676         env_init();
 677         env_load();
 678         debug("boot_os=%s\n", env_get("boot_os"));
 679         if (env_get_yesno("boot_os") == 1)
 680                 ret = 0;
 681 #else
 682         /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
 683         i2c_set_bus_num(0);
 684         gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
 685 #endif
 686         if (!ret)
 687                 gsc_boot_wd_disable();
 688
 689         debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
 690         return ret;
 691 }
 692 #endif