board/gateworks/gw_ventana/gw_ventana.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Gateworks Corporation
   4  *
   5  * Author: Tim Harvey <tharvey@gateworks.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/mxc_hdmi.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/sata.h>
  18 #include <asm/mach-imx/spi.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <asm/io.h>
  21 #include <asm/setup.h>
  22 #include <dm.h>
  23 #include <dm/platform_data/serial_mxc.h>
  24 #include <environment.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <fdt_support.h>
  28 #include <fsl_esdhc.h>
  29 #include <jffs2/load_kernel.h>
  30 #include <linux/ctype.h>
  31 #include <miiphy.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <pci.h>
  35 #include <power/pmic.h>
  36 #include <power/ltc3676_pmic.h>
  37 #include <power/pfuze100_pmic.h>
  38 #include <fdt_support.h>
  39 #include <jffs2/load_kernel.h>
  40 #include <spi_flash.h>
  41
  42 #include "gsc.h"
  43 #include "common.h"
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47
  48 /*
  49  * EEPROM board info struct populated by read_eeprom so that we only have to
  50  * read it once.
  51  */
  52 struct ventana_board_info ventana_info;
  53
  54 static int board_type;
  55
  56 /* ENET */
  57 static iomux_v3_cfg_t const enet_pads[] = {
  58         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  66                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  68                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  75                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         /* PHY nRST */
  77         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  78 };
  79
  80 #ifdef CONFIG_CMD_NAND
  81 static iomux_v3_cfg_t const nfc_pads[] = {
  82         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97 };
  98
  99 static void setup_gpmi_nand(void)
 100 {
 101         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 102
 103         /* config gpmi nand iomux */
 104         SETUP_IOMUX_PADS(nfc_pads);
 105
 106         /* config gpmi and bch clock to 100 MHz */
 107         clrsetbits_le32(&mxc_ccm->cs2cdr,
 108                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 109                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 110                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 111                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 112                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 113                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 114
 115         /* enable gpmi and bch clock gating */
 116         setbits_le32(&mxc_ccm->CCGR4,
 117                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 118                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 119                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 120                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 121                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 122
 123         /* enable apbh clock gating */
 124         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 125 }
 126 #endif
 127
 128 static void setup_iomux_enet(int gpio)
 129 {
 130         SETUP_IOMUX_PADS(enet_pads);
 131
 132         /* toggle PHY_RST# */
 133         gpio_request(gpio, "phy_rst#");
 134         gpio_direction_output(gpio, 0);
 135         mdelay(10);
 136         gpio_set_value(gpio, 1);
 137         mdelay(100);
 138 }
 139
 140 #ifdef CONFIG_USB_EHCI_MX6
 141 static iomux_v3_cfg_t const usb_pads[] = {
 142         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 143         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 144         /* OTG PWR */
 145         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 146 };
 147
 148 int board_ehci_hcd_init(int port)
 149 {
 150         int gpio;
 151
 152         SETUP_IOMUX_PADS(usb_pads);
 153
 154         /* Reset USB HUB */
 155         switch (board_type) {
 156         case GW53xx:
 157         case GW552x:
 158                 gpio = (IMX_GPIO_NR(1, 9));
 159                 break;
 160         case GW54proto:
 161         case GW54xx:
 162                 gpio = (IMX_GPIO_NR(1, 16));
 163                 break;
 164         default:
 165                 return 0;
 166         }
 167
 168         /* request and toggle hub rst */
 169         gpio_request(gpio, "usb_hub_rst#");
 170         gpio_direction_output(gpio, 0);
 171         mdelay(2);
 172         gpio_set_value(gpio, 1);
 173
 174         return 0;
 175 }
 176
 177 int board_ehci_power(int port, int on)
 178 {
 179         /* enable OTG VBUS */
 180         if (!port && board_type < GW_UNKNOWN) {
 181                 if (gpio_cfg[board_type].otgpwr_en)
 182                         gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
 183         }
 184         return 0;
 185 }
 186 #endif /* CONFIG_USB_EHCI_MX6 */
 187
 188 #ifdef CONFIG_MXC_SPI
 189 iomux_v3_cfg_t const ecspi1_pads[] = {
 190         /* SS1 */
 191         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 192         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 193         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 194         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 195 };
 196
 197 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 198 {
 199         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 200 }
 201
 202 static void setup_spi(void)
 203 {
 204         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 205         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 206         SETUP_IOMUX_PADS(ecspi1_pads);
 207 }
 208 #endif
 209
 210 /* configure eth0 PHY board-specific LED behavior */
 211 int board_phy_config(struct phy_device *phydev)
 212 {
 213         unsigned short val;
 214
 215         /* Marvel 88E1510 */
 216         if (phydev->phy_id == 0x1410dd1) {
 217                 /*
 218                  * Page 3, Register 16: LED[2:0] Function Control Register
 219                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 220                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 221                  */
 222                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 223                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 224                 val &= 0xff00;
 225                 val |= 0x0017;
 226                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 227                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 228         }
 229
 230         /* TI DP83867 */
 231         else if (phydev->phy_id == 0x2000a231) {
 232                 /* configure register 0x170 for ref CLKOUT */
 233                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
 234                 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
 235                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
 236                 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
 237                 val &= ~0x1f00;
 238                 val |= 0x0b00; /* chD tx clock*/
 239                 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
 240         }
 241
 242         if (phydev->drv->config)
 243                 phydev->drv->config(phydev);
 244
 245         return 0;
 246 }
 247
 248 #ifdef CONFIG_MV88E61XX_SWITCH
 249 int mv88e61xx_hw_reset(struct phy_device *phydev)
 250 {
 251         struct mii_dev *bus = phydev->bus;
 252
 253         /* GPIO[0] output, CLK125 */
 254         debug("enabling RGMII_REFCLK\n");
 255         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 256                    0x1a /*MV_SCRATCH_MISC*/,
 257                    (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
 258         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 259                    0x1a /*MV_SCRATCH_MISC*/,
 260                    (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
 261
 262         /* RGMII delay - Physical Control register bit[15:14] */
 263         debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
 264         /* forced 1000mbps full-duplex link */
 265         bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
 266         phydev->autoneg = AUTONEG_DISABLE;
 267         phydev->speed = SPEED_1000;
 268         phydev->duplex = DUPLEX_FULL;
 269
 270         /* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
 271         bus->write(bus, 0x10, 0, 0x16, 0x8088);
 272         bus->write(bus, 0x11, 0, 0x16, 0x8088);
 273         bus->write(bus, 0x12, 0, 0x16, 0x8088);
 274         bus->write(bus, 0x13, 0, 0x16, 0x8088);
 275
 276         return 0;
 277 }
 278 #endif // CONFIG_MV88E61XX_SWITCH
 279
 280 int board_eth_init(bd_t *bis)
 281 {
 282 #ifdef CONFIG_FEC_MXC
 283         struct ventana_board_info *info = &ventana_info;
 284
 285         if (test_bit(EECONFIG_ETH0, info->config)) {
 286                 setup_iomux_enet(GP_PHY_RST);
 287                 cpu_eth_init(bis);
 288         }
 289 #endif
 290
 291 #ifdef CONFIG_E1000
 292         e1000_initialize(bis);
 293 #endif
 294
 295 #ifdef CONFIG_CI_UDC
 296         /* For otg ethernet*/
 297         usb_eth_initialize(bis);
 298 #endif
 299
 300         /* default to the first detected enet dev */
 301         if (!env_get("ethprime")) {
 302                 struct eth_device *dev = eth_get_dev_by_index(0);
 303                 if (dev) {
 304                         env_set("ethprime", dev->name);
 305                         printf("set ethprime to %s\n", env_get("ethprime"));
 306                 }
 307         }
 308
 309         return 0;
 310 }
 311
 312 #if defined(CONFIG_VIDEO_IPUV3)
 313
 314 static void enable_hdmi(struct display_info_t const *dev)
 315 {
 316         imx_enable_hdmi_phy();
 317 }
 318
 319 static int detect_i2c(struct display_info_t const *dev)
 320 {
 321         return i2c_set_bus_num(dev->bus) == 0 &&
 322                 i2c_probe(dev->addr) == 0;
 323 }
 324
 325 static void enable_lvds(struct display_info_t const *dev)
 326 {
 327         struct iomuxc *iomux = (struct iomuxc *)
 328                                 IOMUXC_BASE_ADDR;
 329
 330         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 331         u32 reg = readl(&iomux->gpr[2]);
 332         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 333         writel(reg, &iomux->gpr[2]);
 334
 335         /* Enable Backlight */
 336         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 337         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 338         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 339         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 340         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 341 }
 342
 343 struct display_info_t const displays[] = {{
 344         /* HDMI Output */
 345         .bus    = -1,
 346         .addr   = 0,
 347         .pixfmt = IPU_PIX_FMT_RGB24,
 348         .detect = detect_hdmi,
 349         .enable = enable_hdmi,
 350         .mode   = {
 351                 .name           = "HDMI",
 352                 .refresh        = 60,
 353                 .xres           = 1024,
 354                 .yres           = 768,
 355                 .pixclock       = 15385,
 356                 .left_margin    = 220,
 357                 .right_margin   = 40,
 358                 .upper_margin   = 21,
 359                 .lower_margin   = 7,
 360                 .hsync_len      = 60,
 361                 .vsync_len      = 10,
 362                 .sync           = FB_SYNC_EXT,
 363                 .vmode          = FB_VMODE_NONINTERLACED
 364 } }, {
 365         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 366         .bus    = 2,
 367         .addr   = 0x4,
 368         .pixfmt = IPU_PIX_FMT_LVDS666,
 369         .detect = detect_i2c,
 370         .enable = enable_lvds,
 371         .mode   = {
 372                 .name           = "Hannstar-XGA",
 373                 .refresh        = 60,
 374                 .xres           = 1024,
 375                 .yres           = 768,
 376                 .pixclock       = 15385,
 377                 .left_margin    = 220,
 378                 .right_margin   = 40,
 379                 .upper_margin   = 21,
 380                 .lower_margin   = 7,
 381                 .hsync_len      = 60,
 382                 .vsync_len      = 10,
 383                 .sync           = FB_SYNC_EXT,
 384                 .vmode          = FB_VMODE_NONINTERLACED
 385 } }, {
 386         /* DLC700JMG-T-4 */
 387         .bus    = 0,
 388         .addr   = 0,
 389         .detect = NULL,
 390         .enable = enable_lvds,
 391         .pixfmt = IPU_PIX_FMT_LVDS666,
 392         .mode   = {
 393                 .name           = "DLC700JMGT4",
 394                 .refresh        = 60,
 395                 .xres           = 1024,         /* 1024x600active pixels */
 396                 .yres           = 600,
 397                 .pixclock       = 15385,        /* 64MHz */
 398                 .left_margin    = 220,
 399                 .right_margin   = 40,
 400                 .upper_margin   = 21,
 401                 .lower_margin   = 7,
 402                 .hsync_len      = 60,
 403                 .vsync_len      = 10,
 404                 .sync           = FB_SYNC_EXT,
 405                 .vmode          = FB_VMODE_NONINTERLACED
 406 } }, {
 407         /* DLC800FIG-T-3 */
 408         .bus    = 0,
 409         .addr   = 0,
 410         .detect = NULL,
 411         .enable = enable_lvds,
 412         .pixfmt = IPU_PIX_FMT_LVDS666,
 413         .mode   = {
 414                 .name           = "DLC800FIGT3",
 415                 .refresh        = 60,
 416                 .xres           = 1024,         /* 1024x768 active pixels */
 417                 .yres           = 768,
 418                 .pixclock       = 15385,        /* 64MHz */
 419                 .left_margin    = 220,
 420                 .right_margin   = 40,
 421                 .upper_margin   = 21,
 422                 .lower_margin   = 7,
 423                 .hsync_len      = 60,
 424                 .vsync_len      = 10,
 425                 .sync           = FB_SYNC_EXT,
 426                 .vmode          = FB_VMODE_NONINTERLACED
 427 } }, {
 428         .bus    = 2,
 429         .addr   = 0x5d,
 430         .detect = detect_i2c,
 431         .enable = enable_lvds,
 432         .pixfmt = IPU_PIX_FMT_LVDS666,
 433         .mode   = {
 434                 .name           = "Z101WX01",
 435                 .refresh        = 60,
 436                 .xres           = 1280,
 437                 .yres           = 800,
 438                 .pixclock       = 15385,        /* 64MHz */
 439                 .left_margin    = 220,
 440                 .right_margin   = 40,
 441                 .upper_margin   = 21,
 442                 .lower_margin   = 7,
 443                 .hsync_len      = 60,
 444                 .vsync_len      = 10,
 445                 .sync           = FB_SYNC_EXT,
 446                 .vmode          = FB_VMODE_NONINTERLACED
 447         }
 448 },
 449 };
 450 size_t display_count = ARRAY_SIZE(displays);
 451
 452 static void setup_display(void)
 453 {
 454         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 455         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 456         int reg;
 457
 458         enable_ipu_clock();
 459         imx_setup_hdmi();
 460         /* Turn on LDB0,IPU,IPU DI0 clocks */
 461         reg = __raw_readl(&mxc_ccm->CCGR3);
 462         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 463         writel(reg, &mxc_ccm->CCGR3);
 464
 465         /* set LDB0, LDB1 clk select to 011/011 */
 466         reg = readl(&mxc_ccm->cs2cdr);
 467         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 468                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 469         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 470               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 471         writel(reg, &mxc_ccm->cs2cdr);
 472
 473         reg = readl(&mxc_ccm->cscmr2);
 474         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 475         writel(reg, &mxc_ccm->cscmr2);
 476
 477         reg = readl(&mxc_ccm->chsccdr);
 478         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 479                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 480         writel(reg, &mxc_ccm->chsccdr);
 481
 482         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 483              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 484              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 485              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 486              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 487              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 488              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 489              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 490              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 491         writel(reg, &iomux->gpr[2]);
 492
 493         reg = readl(&iomux->gpr[3]);
 494         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 495             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 496                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 497         writel(reg, &iomux->gpr[3]);
 498
 499         /* LVDS Backlight GPIO on LVDS connector - output low */
 500         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 501         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 502 }
 503 #endif /* CONFIG_VIDEO_IPUV3 */
 504
 505 /* setup board specific PMIC */
 506 int power_init_board(void)
 507 {
 508         setup_pmic();
 509         return 0;
 510 }
 511
 512 #if defined(CONFIG_CMD_PCI)
 513 int imx6_pcie_toggle_reset(void)
 514 {
 515         if (board_type < GW_UNKNOWN) {
 516                 uint pin = gpio_cfg[board_type].pcie_rst;
 517                 gpio_request(pin, "pci_rst#");
 518                 gpio_direction_output(pin, 0);
 519                 mdelay(50);
 520                 gpio_direction_output(pin, 1);
 521         }
 522         return 0;
 523 }
 524
 525 /*
 526  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 527  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 528  * properly and assert reset for 100ms.
 529  */
 530 #define MAX_PCI_DEVS    32
 531 struct pci_dev {
 532         pci_dev_t devfn;
 533         unsigned short vendor;
 534         unsigned short device;
 535         unsigned short class;
 536         unsigned short busno; /* subbordinate busno */
 537         struct pci_dev *ppar;
 538 };
 539 struct pci_dev pci_devs[MAX_PCI_DEVS];
 540 int pci_devno;
 541 int pci_bridgeno;
 542
 543 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 544                          unsigned short vendor, unsigned short device,
 545                          unsigned short class)
 546 {
 547         int i;
 548         u32 dw;
 549         struct pci_dev *pdev = &pci_devs[pci_devno++];
 550
 551         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 552               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 553
 554         /* store array of devs for later use in device-tree fixup */
 555         pdev->devfn = dev;
 556         pdev->vendor = vendor;
 557         pdev->device = device;
 558         pdev->class = class;
 559         pdev->ppar = NULL;
 560         if (class == PCI_CLASS_BRIDGE_PCI)
 561                 pdev->busno = ++pci_bridgeno;
 562         else
 563                 pdev->busno = 0;
 564
 565         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 566         if (PCI_BUS(dev) == 0)
 567                 pdev->devfn = 0;
 568
 569         /* find dev's parent */
 570         for (i = 0; i < pci_devno; i++) {
 571                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 572                         pdev->ppar = &pci_devs[i];
 573                         break;
 574                 }
 575         }
 576
 577         /* assert downstream PERST# */
 578         if (vendor == PCI_VENDOR_ID_PLX &&
 579             (device & 0xfff0) == 0x8600 &&
 580             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 581                 debug("configuring PLX 860X downstream PERST#\n");
 582                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 583                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 584                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 585
 586                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 587                 dw |= 0xfe;   /* GPIO1-7 output high */
 588                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 589
 590                 mdelay(100);
 591         }
 592 }
 593 #endif /* CONFIG_CMD_PCI */
 594
 595 #ifdef CONFIG_SERIAL_TAG
 596 /*
 597  * called when setting up ATAGS before booting kernel
 598  * populate serialnum from the following (in order of priority):
 599  *   serial# env var
 600  *   eeprom
 601  */
 602 void get_board_serial(struct tag_serialnr *serialnr)
 603 {
 604         char *serial = env_get("serial#");
 605
 606         if (serial) {
 607                 serialnr->high = 0;
 608                 serialnr->low = simple_strtoul(serial, NULL, 10);
 609         } else if (ventana_info.model[0]) {
 610                 serialnr->high = 0;
 611                 serialnr->low = ventana_info.serial;
 612         } else {
 613                 serialnr->high = 0;
 614                 serialnr->low = 0;
 615         }
 616 }
 617 #endif
 618
 619 /*
 620  * Board Support
 621  */
 622
 623 int board_early_init_f(void)
 624 {
 625         setup_iomux_uart();
 626
 627 #if defined(CONFIG_VIDEO_IPUV3)
 628         setup_display();
 629 #endif
 630         return 0;
 631 }
 632
 633 int dram_init(void)
 634 {
 635         gd->ram_size = imx_ddr_size();
 636         return 0;
 637 }
 638
 639 int board_init(void)
 640 {
 641         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 642
 643         clrsetbits_le32(&iomuxc_regs->gpr[1],
 644                         IOMUXC_GPR1_OTG_ID_MASK,
 645                         IOMUXC_GPR1_OTG_ID_GPIO1);
 646
 647         /* address of linux boot parameters */
 648         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 649
 650         /* read Gateworks EEPROM into global struct (used later) */
 651         setup_ventana_i2c(0);
 652         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 653
 654 #ifdef CONFIG_CMD_NAND
 655         if (gpio_cfg[board_type].nand)
 656                 setup_gpmi_nand();
 657 #endif
 658 #ifdef CONFIG_MXC_SPI
 659         setup_spi();
 660 #endif
 661         setup_ventana_i2c(1);
 662         setup_ventana_i2c(2);
 663
 664 #ifdef CONFIG_SATA
 665         setup_sata();
 666 #endif
 667
 668         setup_iomux_gpio(board_type, &ventana_info);
 669
 670         return 0;
 671 }
 672
 673 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 674 /*
 675  * called during late init (after relocation and after board_init())
 676  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 677  * EEPROM read.
 678  */
 679 int checkboard(void)
 680 {
 681         struct ventana_board_info *info = &ventana_info;
 682         unsigned char buf[4];
 683         const char *p;
 684         int quiet; /* Quiet or minimal output mode */
 685
 686         quiet = 0;
 687         p = env_get("quiet");
 688         if (p)
 689                 quiet = simple_strtol(p, NULL, 10);
 690         else
 691                 env_set("quiet", "0");
 692
 693         puts("\nGateworks Corporation Copyright 2014\n");
 694         if (info->model[0]) {
 695                 printf("Model: %s\n", info->model);
 696                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 697                        info->mfgdate[0], info->mfgdate[1],
 698                        info->mfgdate[2], info->mfgdate[3]);
 699                 printf("Serial:%d\n", info->serial);
 700         } else {
 701                 puts("Invalid EEPROM - board will not function fully\n");
 702         }
 703         if (quiet)
 704                 return 0;
 705
 706         /* Display GSC firmware revision/CRC/status */
 707         gsc_info(0);
 708
 709         /* Display RTC */
 710         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 711                 printf("RTC:   %d\n",
 712                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 713         }
 714
 715         return 0;
 716 }
 717 #endif
 718
 719 #ifdef CONFIG_CMD_BMODE
 720 /*
 721  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 722  * see Table 8-11 and Table 5-9
 723  *  BOOT_CFG1[7] = 1 (boot from NAND)
 724  *  BOOT_CFG1[5] = 0 - raw NAND
 725  *  BOOT_CFG1[4] = 0 - default pad settings
 726  *  BOOT_CFG1[3:2] = 00 - devices = 1
 727  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 728  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 729  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 730  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 731  */
 732 static const struct boot_mode board_boot_modes[] = {
 733         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 734         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 735         { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
 736         { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
 737         { NULL, 0 },
 738 };
 739 #endif
 740
 741 /* late init */
 742 int misc_init_r(void)
 743 {
 744         struct ventana_board_info *info = &ventana_info;
 745         char buf[256];
 746         int i;
 747
 748         /* set env vars based on EEPROM data */
 749         if (ventana_info.model[0]) {
 750                 char str[16], fdt[36];
 751                 char *p;
 752                 const char *cputype = "";
 753
 754                 /*
 755                  * FDT name will be prefixed with CPU type.  Three versions
 756                  * will be created each increasingly generic and bootloader
 757                  * env scripts will try loading each from most specific to
 758                  * least.
 759                  */
 760                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 761                     is_cpu_type(MXC_CPU_MX6D))
 762                         cputype = "imx6q";
 763                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 764                          is_cpu_type(MXC_CPU_MX6SOLO))
 765                         cputype = "imx6dl";
 766                 env_set("soctype", cputype);
 767                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 768                         env_set("flash_layout", "large");
 769                 else
 770                         env_set("flash_layout", "normal");
 771                 memset(str, 0, sizeof(str));
 772                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 773                         str[i] = tolower(info->model[i]);
 774                 env_set("model", str);
 775                 if (!env_get("fdt_file")) {
 776                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 777                         env_set("fdt_file", fdt);
 778                 }
 779                 p = strchr(str, '-');
 780                 if (p) {
 781                         *p++ = 0;
 782
 783                         env_set("model_base", str);
 784                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 785                         env_set("fdt_file1", fdt);
 786                         if (board_type != GW551x &&
 787                             board_type != GW552x &&
 788                             board_type != GW553x &&
 789                             board_type != GW560x)
 790                                 str[4] = 'x';
 791                         str[5] = 'x';
 792                         str[6] = 0;
 793                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 794                         env_set("fdt_file2", fdt);
 795                 }
 796
 797                 /* initialize env from EEPROM */
 798                 if (test_bit(EECONFIG_ETH0, info->config) &&
 799                     !env_get("ethaddr")) {
 800                         eth_env_set_enetaddr("ethaddr", info->mac0);
 801                 }
 802                 if (test_bit(EECONFIG_ETH1, info->config) &&
 803                     !env_get("eth1addr")) {
 804                         eth_env_set_enetaddr("eth1addr", info->mac1);
 805                 }
 806
 807                 /* board serial-number */
 808                 sprintf(str, "%6d", info->serial);
 809                 env_set("serial#", str);
 810
 811                 /* memory MB */
 812                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 813                 env_set("mem_mb", str);
 814         }
 815
 816         /* Set a non-initialized hwconfig based on board configuration */
 817         if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
 818                 buf[0] = 0;
 819                 if (gpio_cfg[board_type].rs232_en)
 820                         strcat(buf, "rs232;");
 821                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 822                         char buf1[32];
 823                         sprintf(buf1, "dio%d:mode=gpio;", i);
 824                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 825                                 strcat(buf, buf1);
 826                 }
 827                 env_set("hwconfig", buf);
 828         }
 829
 830         /* setup baseboard specific GPIO based on board and env */
 831         setup_board_gpio(board_type, info);
 832
 833 #ifdef CONFIG_CMD_BMODE
 834         add_board_boot_modes(board_boot_modes);
 835 #endif
 836
 837         /* disable boot watchdog */
 838         gsc_boot_wd_disable();
 839
 840         return 0;
 841 }
 842
 843 #ifdef CONFIG_OF_BOARD_SETUP
 844
 845 static int ft_sethdmiinfmt(void *blob, char *mode)
 846 {
 847         int off;
 848
 849         if (!mode)
 850                 return -EINVAL;
 851
 852         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 853         if (off < 0)
 854                 return off;
 855
 856         if (0 == strcasecmp(mode, "yuv422bt656")) {
 857                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 858                              0x00, 0x00, 0x00 };
 859                 mode = "422_ccir";
 860                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 861                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 862                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 863                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 864                 printf("   set HDMI input mode to %s\n", mode);
 865         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 866                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 867                              0x82, 0x81, 0x00 };
 868                 mode = "422_smp";
 869                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 870                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 871                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 872                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 873                 printf("   set HDMI input mode to %s\n", mode);
 874         } else {
 875                 return -EINVAL;
 876         }
 877
 878         return 0;
 879 }
 880
 881 /* enable a property of a node if the node is found */
 882 static inline void ft_enable_path(void *blob, const char *path)
 883 {
 884         int i = fdt_path_offset(blob, path);
 885         if (i >= 0) {
 886                 debug("enabling %s\n", path);
 887                 fdt_status_okay(blob, i);
 888         }
 889 }
 890
 891 /* remove a property of a node if the node is found */
 892 static inline void ft_delprop_path(void *blob, const char *path,
 893                                    const char *name)
 894 {
 895         int i = fdt_path_offset(blob, path);
 896         if (i) {
 897                 debug("removing %s/%s\n", path, name);
 898                 fdt_delprop(blob, i, name);
 899         }
 900 }
 901
 902 #if defined(CONFIG_CMD_PCI)
 903 #define PCI_ID(x) ( \
 904         (PCI_BUS(x->devfn)<<16)| \
 905         (PCI_DEV(x->devfn)<<11)| \
 906         (PCI_FUNC(x->devfn)<<8) \
 907         )
 908 #define PCIE_PATH       "/soc/pcie@0x01000000"
 909 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 910 {
 911         uint32_t reg[5];
 912         char node[32];
 913         int np;
 914
 915         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 916                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 917
 918         np = fdt_subnode_offset(blob, par, node);
 919         if (np >= 0)
 920                 return np;
 921         np = fdt_add_subnode(blob, par, node);
 922         if (np < 0) {
 923                 printf("   %s failed: no space\n", __func__);
 924                 return np;
 925         }
 926
 927         memset(reg, 0, sizeof(reg));
 928         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 929         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 930
 931         return np;
 932 }
 933
 934 /* build a path of nested PCI devs for all bridges passed through */
 935 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 936 {
 937         struct pci_dev *bridges[MAX_PCI_DEVS];
 938         int k, np;
 939
 940         /* build list of parents */
 941         np = fdt_path_offset(blob, PCIE_PATH);
 942         if (np < 0)
 943                 return np;
 944
 945         k = 0;
 946         while (dev) {
 947                 bridges[k++] = dev;
 948                 dev = dev->ppar;
 949         };
 950
 951         /* now add them the to DT in reverse order */
 952         while (k--) {
 953                 np = fdt_add_pci_node(blob, np, bridges[k]);
 954                 if (np < 0)
 955                         break;
 956         }
 957
 958         return np;
 959 }
 960
 961 /*
 962  * The GW16082 has a hardware errata errata such that it's
 963  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 964  * of this normal PCI interrupt swizzling will not work so we will
 965  * provide an irq-map via device-tree.
 966  */
 967 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 968 {
 969         int len;
 970         int host;
 971         uint32_t imap_new[8*4*4];
 972         const uint32_t *imap;
 973         uint32_t irq[4];
 974         uint32_t reg[4];
 975         int i;
 976
 977         /* build irq-map based on host controllers map */
 978         host = fdt_path_offset(blob, PCIE_PATH);
 979         if (host < 0) {
 980                 printf("   %s failed: missing host\n", __func__);
 981                 return host;
 982         }
 983
 984         /* use interrupt data from root complex's node */
 985         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 986         if (!imap || len != 128) {
 987                 printf("   %s failed: invalid interrupt-map\n",
 988                        __func__);
 989                 return -FDT_ERR_NOTFOUND;
 990         }
 991
 992         /* obtain irq's of host controller in pin order */
 993         for (i = 0; i < 4; i++)
 994                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 995
 996         /*
 997          * determine number of swizzles necessary:
 998          *   For each bridge we pass through we need to swizzle
 999          *   the number of the slot we are on.
1000          */
1001         struct pci_dev *d;
1002         int b;
1003         b = 0;
1004         d = dev->ppar;
1005         while(d && d->ppar) {
1006                 b += PCI_DEV(d->devfn);
1007                 d = d->ppar;
1008         }
1009
1010         /* create new irq mappings for slots12-15
1011          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
1012          * J3    AD28    12     INTD      INTA
1013          * J4    AD29    13     INTC      INTD
1014          * J5    AD30    14     INTB      INTC
1015          * J2    AD31    15     INTA      INTB
1016          */
1017         for (i = 0; i < 4; i++) {
1018                 /* addr matches bus:dev:func */
1019                 u32 addr = dev->busno << 16 | (12+i) << 11;
1020
1021                 /* default cells from root complex */
1022                 memcpy(&imap_new[i*32], imap, 128);
1023                 /* first cell is PCI device address (BDF) */
1024                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1025                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1026                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1027                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1028                 /* third cell is pin */
1029                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1030                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1031                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1032                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1033                 /* sixth cell is relative interrupt */
1034                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1035                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1036                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1037                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1038         }
1039         fdt_setprop(blob, np, "interrupt-map", imap_new,
1040                     sizeof(imap_new));
1041         reg[0] = cpu_to_fdt32(0xfff00);
1042         reg[1] = 0;
1043         reg[2] = 0;
1044         reg[3] = cpu_to_fdt32(0x7);
1045         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1046         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1047         fdt_setprop_string(blob, np, "device_type", "pci");
1048         fdt_setprop_cell(blob, np, "#address-cells", 3);
1049         fdt_setprop_cell(blob, np, "#size-cells", 2);
1050         printf("   Added custom interrupt-map for GW16082\n");
1051
1052         return 0;
1053 }
1054
1055 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1056 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1057 {
1058         char *tmp, *end;
1059         char mac[16];
1060         unsigned char mac_addr[6];
1061         int j;
1062
1063         sprintf(mac, "eth1addr");
1064         tmp = env_get(mac);
1065         if (tmp) {
1066                 for (j = 0; j < 6; j++) {
1067                         mac_addr[j] = tmp ?
1068                                       simple_strtoul(tmp, &end,16) : 0;
1069                         if (tmp)
1070                                 tmp = (*end) ? end+1 : end;
1071                 }
1072                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1073                             sizeof(mac_addr));
1074                 printf("   Added mac addr for eth1\n");
1075                 return 0;
1076         }
1077
1078         return -1;
1079 }
1080
1081 /*
1082  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1083  * we will walk the PCI bus and add bridge nodes up to the device receiving
1084  * the fixup.
1085  */
1086 void ft_board_pci_fixup(void *blob, bd_t *bd)
1087 {
1088         int i, np;
1089         struct pci_dev *dev;
1090
1091         for (i = 0; i < pci_devno; i++) {
1092                 dev = &pci_devs[i];
1093
1094                 /*
1095                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1096                  * an EEPROM at i2c1-0x50.
1097                  */
1098                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1099                     (dev->device == 0x8240) &&
1100                     (i2c_set_bus_num(1) == 0) &&
1101                     (i2c_probe(0x50) == 0))
1102                 {
1103                         np = fdt_add_pci_path(blob, dev);
1104                         if (np > 0)
1105                                 fdt_fixup_gw16082(blob, np, dev);
1106                 }
1107
1108                 /* ethernet1 mac address */
1109                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1110                          (dev->device == 0x4380))
1111                 {
1112                         np = fdt_add_pci_path(blob, dev);
1113                         if (np > 0)
1114                                 fdt_fixup_sky2(blob, np, dev);
1115                 }
1116         }
1117 }
1118 #endif /* if defined(CONFIG_CMD_PCI) */
1119
1120 void ft_board_wdog_fixup(void *blob, const char *path)
1121 {
1122         ft_delprop_path(blob, path, "ext-reset-output");
1123         ft_delprop_path(blob, path, "fsl,ext-reset-output");
1124 }
1125
1126 /*
1127  * called prior to booting kernel or by 'fdt boardsetup' command
1128  *
1129  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1130  *  - mtd partitions based on mtdparts/mtdids env
1131  *  - system-serial (board serial num from EEPROM)
1132  *  - board (full model from EEPROM)
1133  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1134  */
1135 #define UART1_PATH      "/soc/aips-bus@02100000/serial@021ec000"
1136 #define WDOG1_PATH      "/soc/aips-bus@02000000/wdog@020bc000"
1137 #define WDOG2_PATH      "/soc/aips-bus@02000000/wdog@020c0000"
1138 #define GPIO3_PATH      "/soc/aips-bus@02000000/gpio@020a4000"
1139 int ft_board_setup(void *blob, bd_t *bd)
1140 {
1141         struct ventana_board_info *info = &ventana_info;
1142         struct ventana_eeprom_config *cfg;
1143         static const struct node_info nodes[] = {
1144                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1145                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1146         };
1147         const char *model = env_get("model");
1148         const char *display = env_get("display");
1149         int i;
1150         char rev = 0;
1151
1152         /* determine board revision */
1153         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1154                 if (ventana_info.model[i] >= 'A') {
1155                         rev = ventana_info.model[i];
1156                         break;
1157                 }
1158         }
1159
1160         if (env_get("fdt_noauto")) {
1161                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1162                 return 0;
1163         }
1164
1165         if (test_bit(EECONFIG_NAND, info->config)) {
1166                 /* Update partition nodes using info from mtdparts env var */
1167                 puts("   Updating MTD partitions...\n");
1168                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1169         }
1170
1171         /* Update display timings from display env var */
1172         if (display) {
1173                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1174                                       display) >= 0)
1175                         printf("   Set display timings for %s...\n", display);
1176         }
1177
1178         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1179
1180         /* board serial number */
1181         fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1182                     strlen(env_get("serial#")) + 1);
1183
1184         /* board (model contains model from device-tree) */
1185         fdt_setprop(blob, 0, "board", info->model,
1186                     strlen((const char *)info->model) + 1);
1187
1188         /* set desired digital video capture format */
1189         ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1190
1191         /*
1192          * Board model specific fixups
1193          */
1194         switch (board_type) {
1195         case GW51xx:
1196                 /*
1197                  * disable wdog node for GW51xx-A/B to work around
1198                  * errata causing wdog timer to be unreliable.
1199                  */
1200                 if (rev >= 'A' && rev < 'C') {
1201                         i = fdt_path_offset(blob, WDOG1_PATH);
1202                         if (i)
1203                                 fdt_status_disabled(blob, i);
1204                 }
1205
1206                 /* GW51xx-E adds WDOG1_B external reset */
1207                 if (rev < 'E')
1208                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1209                 break;
1210
1211         case GW52xx:
1212                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1213                 if (info->model[4] == '2') {
1214                         u32 handle = 0;
1215                         u32 *range = NULL;
1216
1217                         i = fdt_node_offset_by_compatible(blob, -1,
1218                                                           "fsl,imx6q-pcie");
1219                         if (i)
1220                                 range = (u32 *)fdt_getprop(blob, i,
1221                                                            "reset-gpio", NULL);
1222
1223                         if (range) {
1224                                 i = fdt_path_offset(blob, GPIO3_PATH);
1225                                 if (i)
1226                                         handle = fdt_get_phandle(blob, i);
1227                                 if (handle) {
1228                                         range[0] = cpu_to_fdt32(handle);
1229                                         range[1] = cpu_to_fdt32(23);
1230                                 }
1231                         }
1232
1233                         /* these have broken usd_vsel */
1234                         if (strstr((const char *)info->model, "SP318-B") ||
1235                             strstr((const char *)info->model, "SP331-B"))
1236                                 gpio_cfg[board_type].usd_vsel = 0;
1237
1238                         /* GW522x-B adds WDOG1_B external reset */
1239                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1240                 }
1241
1242                 /* GW520x-E adds WDOG1_B external reset */
1243                 else if (info->model[4] == '0' && rev < 'E')
1244                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1245                 break;
1246
1247         case GW53xx:
1248                 /* GW53xx-E adds WDOG1_B external reset */
1249                 if (rev < 'E')
1250                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1251                 break;
1252
1253         case GW54xx:
1254                 /*
1255                  * disable serial2 node for GW54xx for compatibility with older
1256                  * 3.10.x kernel that improperly had this node enabled in the DT
1257                  */
1258                 i = fdt_path_offset(blob, UART1_PATH);
1259                 if (i)
1260                         fdt_del_node(blob, i);
1261
1262                 /* GW54xx-E adds WDOG2_B external reset */
1263                 if (rev < 'E')
1264                         ft_board_wdog_fixup(blob, WDOG2_PATH);
1265                 break;
1266
1267         case GW551x:
1268                 /*
1269                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1270                  * causing non functional digital video in (it is not hooked up)
1271                  */
1272                 if (rev == 'A') {
1273                         u32 *range = NULL;
1274                         int len;
1275                         const u32 *handle = NULL;
1276
1277                         i = fdt_node_offset_by_compatible(blob, -1,
1278                                                 "fsl,imx-tda1997x-video");
1279                         if (i)
1280                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1281                                                      NULL);
1282                         if (handle)
1283                                 i = fdt_node_offset_by_phandle(blob,
1284                                                         fdt32_to_cpu(*handle));
1285                         if (i)
1286                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1287                                                            &len);
1288                         if (range) {
1289                                 len /= sizeof(u32);
1290                                 for (i = 0; i < len; i += 6) {
1291                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1292                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1293                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1294                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1295                                             mux_reg == 0x260 &&
1296                                             conf_reg == 0x630)
1297                                                 range[i+3] = cpu_to_fdt32(0x5);
1298                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1299                                                  mux_reg == 0x08c &&
1300                                                  conf_reg == 0x3a0)
1301                                                 range[i+3] = cpu_to_fdt32(0x5);
1302                                 }
1303                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1304                                                     len);
1305                         }
1306
1307                         /* set BT656 video format */
1308                         ft_sethdmiinfmt(blob, "yuv422bt656");
1309                 }
1310
1311                 /* GW551x-C adds WDOG1_B external reset */
1312                 if (rev < 'C')
1313                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1314                 break;
1315         }
1316
1317         /* Configure DIO */
1318         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1319                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1320                 char arg[10];
1321
1322                 sprintf(arg, "dio%d", i);
1323                 if (!hwconfig(arg))
1324                         continue;
1325                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1326                 {
1327                         char path[48];
1328                         sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1329                                 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1330                         printf("   Enabling pwm%d for DIO%d\n",
1331                                cfg->pwm_param, i);
1332                         ft_enable_path(blob, path);
1333                 }
1334         }
1335
1336         /* remove no-1-8-v if UHS-I support is present */
1337         if (gpio_cfg[board_type].usd_vsel) {
1338                 debug("Enabling UHS-I support\n");
1339                 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1340                                 "no-1-8-v");
1341         }
1342
1343 #if defined(CONFIG_CMD_PCI)
1344         if (!env_get("nopcifixup"))
1345                 ft_board_pci_fixup(blob, bd);
1346 #endif
1347
1348         /*
1349          * Peripheral Config:
1350          *  remove nodes by alias path if EEPROM config tells us the
1351          *  peripheral is not loaded on the board.
1352          */
1353         if (env_get("fdt_noconfig")) {
1354                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1355                 return 0;
1356         }
1357         cfg = econfig;
1358         while (cfg->name) {
1359                 if (!test_bit(cfg->bit, info->config)) {
1360                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1361                                                cfg->dtalias : cfg->name);
1362                 }
1363                 cfg++;
1364         }
1365
1366         return 0;
1367 }
1368 #endif /* CONFIG_OF_BOARD_SETUP */
1369
1370 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1371         .reg = (struct mxc_uart *)UART2_BASE,
1372 };
1373
1374 U_BOOT_DEVICE(ventana_serial) = {
1375         .name   = "serial_mxc",
1376         .platdata = &ventana_mxc_serial_plat,
1377 };