board/gateworks/gw_ventana/gw_ventana.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Gateworks Corporation
   4  *
   5  * Author: Tim Harvey <tharvey@gateworks.com>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <net.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/arch/mxc_hdmi.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/sata.h>
  21 #include <asm/mach-imx/spi.h>
  22 #include <asm/mach-imx/video.h>
  23 #include <asm/io.h>
  24 #include <asm/setup.h>
  25 #include <dm.h>
  26 #include <dm/platform_data/serial_mxc.h>
  27 #include <env.h>
  28 #include <hwconfig.h>
  29 #include <i2c.h>
  30 #include <fdt_support.h>
  31 #include <fsl_esdhc_imx.h>
  32 #include <jffs2/load_kernel.h>
  33 #include <linux/ctype.h>
  34 #include <miiphy.h>
  35 #include <mtd_node.h>
  36 #include <netdev.h>
  37 #include <pci.h>
  38 #include <linux/libfdt.h>
  39 #include <power/pmic.h>
  40 #include <power/ltc3676_pmic.h>
  41 #include <power/pfuze100_pmic.h>
  42 #include <fdt_support.h>
  43 #include <jffs2/load_kernel.h>
  44 #include <spi_flash.h>
  45
  46 #include "gsc.h"
  47 #include "common.h"
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51
  52 /*
  53  * EEPROM board info struct populated by read_eeprom so that we only have to
  54  * read it once.
  55  */
  56 struct ventana_board_info ventana_info;
  57
  58 static int board_type;
  59
  60 /* ENET */
  61 static iomux_v3_cfg_t const enet_pads[] = {
  62         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  70                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  72                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  79                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         /* PHY nRST */
  81         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  82 };
  83
  84 #ifdef CONFIG_CMD_NAND
  85 static iomux_v3_cfg_t const nfc_pads[] = {
  86         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 100         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 101 };
 102
 103 static void setup_gpmi_nand(void)
 104 {
 105         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 106
 107         /* config gpmi nand iomux */
 108         SETUP_IOMUX_PADS(nfc_pads);
 109
 110         /* config gpmi and bch clock to 100 MHz */
 111         clrsetbits_le32(&mxc_ccm->cs2cdr,
 112                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 113                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 114                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 115                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 116                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 117                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 118
 119         /* enable gpmi and bch clock gating */
 120         setbits_le32(&mxc_ccm->CCGR4,
 121                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 122                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 123                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 124                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 125                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 126
 127         /* enable apbh clock gating */
 128         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 129 }
 130 #endif
 131
 132 static void setup_iomux_enet(int gpio)
 133 {
 134         SETUP_IOMUX_PADS(enet_pads);
 135
 136         /* toggle PHY_RST# */
 137         gpio_request(gpio, "phy_rst#");
 138         gpio_direction_output(gpio, 0);
 139         mdelay(10);
 140         gpio_set_value(gpio, 1);
 141         mdelay(100);
 142 }
 143
 144 #ifdef CONFIG_USB_EHCI_MX6
 145 static iomux_v3_cfg_t const usb_pads[] = {
 146         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 147         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 148         /* OTG PWR */
 149         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 150 };
 151
 152 int board_ehci_hcd_init(int port)
 153 {
 154         int gpio;
 155
 156         SETUP_IOMUX_PADS(usb_pads);
 157
 158         /* Reset USB HUB */
 159         switch (board_type) {
 160         case GW53xx:
 161         case GW552x:
 162         case GW5906:
 163                 gpio = (IMX_GPIO_NR(1, 9));
 164                 break;
 165         case GW54proto:
 166         case GW54xx:
 167                 gpio = (IMX_GPIO_NR(1, 16));
 168                 break;
 169         default:
 170                 return 0;
 171         }
 172
 173         /* request and toggle hub rst */
 174         gpio_request(gpio, "usb_hub_rst#");
 175         gpio_direction_output(gpio, 0);
 176         mdelay(2);
 177         gpio_set_value(gpio, 1);
 178
 179         return 0;
 180 }
 181
 182 int board_ehci_power(int port, int on)
 183 {
 184         /* enable OTG VBUS */
 185         if (!port && board_type < GW_UNKNOWN) {
 186                 if (gpio_cfg[board_type].otgpwr_en)
 187                         gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
 188         }
 189         return 0;
 190 }
 191 #endif /* CONFIG_USB_EHCI_MX6 */
 192
 193 #ifdef CONFIG_MXC_SPI
 194 iomux_v3_cfg_t const ecspi1_pads[] = {
 195         /* SS1 */
 196         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 197         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 198         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 199         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 200 };
 201
 202 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 203 {
 204         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 205 }
 206
 207 static void setup_spi(void)
 208 {
 209         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 210         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 211         SETUP_IOMUX_PADS(ecspi1_pads);
 212 }
 213 #endif
 214
 215 /* configure eth0 PHY board-specific LED behavior */
 216 int board_phy_config(struct phy_device *phydev)
 217 {
 218         unsigned short val;
 219
 220         /* Marvel 88E1510 */
 221         if (phydev->phy_id == 0x1410dd1) {
 222                 /*
 223                  * Page 3, Register 16: LED[2:0] Function Control Register
 224                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 225                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 226                  */
 227                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 228                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 229                 val &= 0xff00;
 230                 val |= 0x0017;
 231                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 232                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 233         }
 234
 235         /* TI DP83867 */
 236         else if (phydev->phy_id == 0x2000a231) {
 237                 /* configure register 0x170 for ref CLKOUT */
 238                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
 239                 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
 240                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
 241                 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
 242                 val &= ~0x1f00;
 243                 val |= 0x0b00; /* chD tx clock*/
 244                 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
 245         }
 246
 247         if (phydev->drv->config)
 248                 phydev->drv->config(phydev);
 249
 250         return 0;
 251 }
 252
 253 #ifdef CONFIG_MV88E61XX_SWITCH
 254 int mv88e61xx_hw_reset(struct phy_device *phydev)
 255 {
 256         struct mii_dev *bus = phydev->bus;
 257
 258         /* GPIO[0] output, CLK125 */
 259         debug("enabling RGMII_REFCLK\n");
 260         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 261                    0x1a /*MV_SCRATCH_MISC*/,
 262                    (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
 263         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 264                    0x1a /*MV_SCRATCH_MISC*/,
 265                    (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
 266
 267         /* RGMII delay - Physical Control register bit[15:14] */
 268         debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
 269         /* forced 1000mbps full-duplex link */
 270         bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
 271         phydev->autoneg = AUTONEG_DISABLE;
 272         phydev->speed = SPEED_1000;
 273         phydev->duplex = DUPLEX_FULL;
 274
 275         /* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
 276         bus->write(bus, 0x10, 0, 0x16, 0x8088);
 277         bus->write(bus, 0x11, 0, 0x16, 0x8088);
 278         bus->write(bus, 0x12, 0, 0x16, 0x8088);
 279         bus->write(bus, 0x13, 0, 0x16, 0x8088);
 280
 281         return 0;
 282 }
 283 #endif // CONFIG_MV88E61XX_SWITCH
 284
 285 int board_eth_init(bd_t *bis)
 286 {
 287 #ifdef CONFIG_FEC_MXC
 288         struct ventana_board_info *info = &ventana_info;
 289
 290         if (test_bit(EECONFIG_ETH0, info->config)) {
 291                 setup_iomux_enet(GP_PHY_RST);
 292                 cpu_eth_init(bis);
 293         }
 294 #endif
 295
 296 #ifdef CONFIG_E1000
 297         e1000_initialize(bis);
 298 #endif
 299
 300 #ifdef CONFIG_CI_UDC
 301         /* For otg ethernet*/
 302         usb_eth_initialize(bis);
 303 #endif
 304
 305         /* default to the first detected enet dev */
 306         if (!env_get("ethprime")) {
 307                 struct eth_device *dev = eth_get_dev_by_index(0);
 308                 if (dev) {
 309                         env_set("ethprime", dev->name);
 310                         printf("set ethprime to %s\n", env_get("ethprime"));
 311                 }
 312         }
 313
 314         return 0;
 315 }
 316
 317 #if defined(CONFIG_VIDEO_IPUV3)
 318
 319 static void enable_hdmi(struct display_info_t const *dev)
 320 {
 321         imx_enable_hdmi_phy();
 322 }
 323
 324 static int detect_i2c(struct display_info_t const *dev)
 325 {
 326         return i2c_set_bus_num(dev->bus) == 0 &&
 327                 i2c_probe(dev->addr) == 0;
 328 }
 329
 330 static void enable_lvds(struct display_info_t const *dev)
 331 {
 332         struct iomuxc *iomux = (struct iomuxc *)
 333                                 IOMUXC_BASE_ADDR;
 334
 335         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 336         u32 reg = readl(&iomux->gpr[2]);
 337         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 338         writel(reg, &iomux->gpr[2]);
 339
 340         /* Enable Backlight */
 341         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 342         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 343         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 344         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 345         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 346 }
 347
 348 struct display_info_t const displays[] = {{
 349         /* HDMI Output */
 350         .bus    = -1,
 351         .addr   = 0,
 352         .pixfmt = IPU_PIX_FMT_RGB24,
 353         .detect = detect_hdmi,
 354         .enable = enable_hdmi,
 355         .mode   = {
 356                 .name           = "HDMI",
 357                 .refresh        = 60,
 358                 .xres           = 1024,
 359                 .yres           = 768,
 360                 .pixclock       = 15385,
 361                 .left_margin    = 220,
 362                 .right_margin   = 40,
 363                 .upper_margin   = 21,
 364                 .lower_margin   = 7,
 365                 .hsync_len      = 60,
 366                 .vsync_len      = 10,
 367                 .sync           = FB_SYNC_EXT,
 368                 .vmode          = FB_VMODE_NONINTERLACED
 369 } }, {
 370         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 371         .bus    = 2,
 372         .addr   = 0x4,
 373         .pixfmt = IPU_PIX_FMT_LVDS666,
 374         .detect = detect_i2c,
 375         .enable = enable_lvds,
 376         .mode   = {
 377                 .name           = "Hannstar-XGA",
 378                 .refresh        = 60,
 379                 .xres           = 1024,
 380                 .yres           = 768,
 381                 .pixclock       = 15385,
 382                 .left_margin    = 220,
 383                 .right_margin   = 40,
 384                 .upper_margin   = 21,
 385                 .lower_margin   = 7,
 386                 .hsync_len      = 60,
 387                 .vsync_len      = 10,
 388                 .sync           = FB_SYNC_EXT,
 389                 .vmode          = FB_VMODE_NONINTERLACED
 390 } }, {
 391         /* DLC700JMG-T-4 */
 392         .bus    = 2,
 393         .addr   = 0x38,
 394         .detect = NULL,
 395         .enable = enable_lvds,
 396         .pixfmt = IPU_PIX_FMT_LVDS666,
 397         .mode   = {
 398                 .name           = "DLC700JMGT4",
 399                 .refresh        = 60,
 400                 .xres           = 1024,         /* 1024x600active pixels */
 401                 .yres           = 600,
 402                 .pixclock       = 15385,        /* 64MHz */
 403                 .left_margin    = 220,
 404                 .right_margin   = 40,
 405                 .upper_margin   = 21,
 406                 .lower_margin   = 7,
 407                 .hsync_len      = 60,
 408                 .vsync_len      = 10,
 409                 .sync           = FB_SYNC_EXT,
 410                 .vmode          = FB_VMODE_NONINTERLACED
 411 } }, {
 412         /* DLC800FIG-T-3 */
 413         .bus    = 2,
 414         .addr   = 0x14,
 415         .detect = NULL,
 416         .enable = enable_lvds,
 417         .pixfmt = IPU_PIX_FMT_LVDS666,
 418         .mode   = {
 419                 .name           = "DLC800FIGT3",
 420                 .refresh        = 60,
 421                 .xres           = 1024,         /* 1024x768 active pixels */
 422                 .yres           = 768,
 423                 .pixclock       = 15385,        /* 64MHz */
 424                 .left_margin    = 220,
 425                 .right_margin   = 40,
 426                 .upper_margin   = 21,
 427                 .lower_margin   = 7,
 428                 .hsync_len      = 60,
 429                 .vsync_len      = 10,
 430                 .sync           = FB_SYNC_EXT,
 431                 .vmode          = FB_VMODE_NONINTERLACED
 432 } }, {
 433         .bus    = 2,
 434         .addr   = 0x5d,
 435         .detect = detect_i2c,
 436         .enable = enable_lvds,
 437         .pixfmt = IPU_PIX_FMT_LVDS666,
 438         .mode   = {
 439                 .name           = "Z101WX01",
 440                 .refresh        = 60,
 441                 .xres           = 1280,
 442                 .yres           = 800,
 443                 .pixclock       = 15385,        /* 64MHz */
 444                 .left_margin    = 220,
 445                 .right_margin   = 40,
 446                 .upper_margin   = 21,
 447                 .lower_margin   = 7,
 448                 .hsync_len      = 60,
 449                 .vsync_len      = 10,
 450                 .sync           = FB_SYNC_EXT,
 451                 .vmode          = FB_VMODE_NONINTERLACED
 452         }
 453 },
 454 };
 455 size_t display_count = ARRAY_SIZE(displays);
 456
 457 static void setup_display(void)
 458 {
 459         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 460         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 461         int reg;
 462
 463         enable_ipu_clock();
 464         imx_setup_hdmi();
 465         /* Turn on LDB0,IPU,IPU DI0 clocks */
 466         reg = __raw_readl(&mxc_ccm->CCGR3);
 467         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 468         writel(reg, &mxc_ccm->CCGR3);
 469
 470         /* set LDB0, LDB1 clk select to 011/011 */
 471         reg = readl(&mxc_ccm->cs2cdr);
 472         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 473                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 474         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 475               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 476         writel(reg, &mxc_ccm->cs2cdr);
 477
 478         reg = readl(&mxc_ccm->cscmr2);
 479         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 480         writel(reg, &mxc_ccm->cscmr2);
 481
 482         reg = readl(&mxc_ccm->chsccdr);
 483         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 484                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 485         writel(reg, &mxc_ccm->chsccdr);
 486
 487         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 488              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 489              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 490              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 491              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 492              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 493              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 494              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 495              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 496         writel(reg, &iomux->gpr[2]);
 497
 498         reg = readl(&iomux->gpr[3]);
 499         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 500             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 501                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 502         writel(reg, &iomux->gpr[3]);
 503
 504         /* LVDS Backlight GPIO on LVDS connector - output low */
 505         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 506         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 507 }
 508 #endif /* CONFIG_VIDEO_IPUV3 */
 509
 510 /* setup board specific PMIC */
 511 int power_init_board(void)
 512 {
 513         setup_pmic();
 514         return 0;
 515 }
 516
 517 #if defined(CONFIG_CMD_PCI)
 518 int imx6_pcie_toggle_reset(void)
 519 {
 520         if (board_type < GW_UNKNOWN) {
 521                 uint pin = gpio_cfg[board_type].pcie_rst;
 522                 gpio_request(pin, "pci_rst#");
 523                 gpio_direction_output(pin, 0);
 524                 mdelay(50);
 525                 gpio_direction_output(pin, 1);
 526         }
 527         return 0;
 528 }
 529
 530 /*
 531  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 532  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 533  * properly and assert reset for 100ms.
 534  */
 535 #define MAX_PCI_DEVS    32
 536 struct pci_dev {
 537         pci_dev_t devfn;
 538         unsigned short vendor;
 539         unsigned short device;
 540         unsigned short class;
 541         unsigned short busno; /* subbordinate busno */
 542         struct pci_dev *ppar;
 543 };
 544 struct pci_dev pci_devs[MAX_PCI_DEVS];
 545 int pci_devno;
 546 int pci_bridgeno;
 547
 548 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 549                          unsigned short vendor, unsigned short device,
 550                          unsigned short class)
 551 {
 552         int i;
 553         u32 dw;
 554         struct pci_dev *pdev = &pci_devs[pci_devno++];
 555
 556         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 557               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 558
 559         /* store array of devs for later use in device-tree fixup */
 560         pdev->devfn = dev;
 561         pdev->vendor = vendor;
 562         pdev->device = device;
 563         pdev->class = class;
 564         pdev->ppar = NULL;
 565         if (class == PCI_CLASS_BRIDGE_PCI)
 566                 pdev->busno = ++pci_bridgeno;
 567         else
 568                 pdev->busno = 0;
 569
 570         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 571         if (PCI_BUS(dev) == 0)
 572                 pdev->devfn = 0;
 573
 574         /* find dev's parent */
 575         for (i = 0; i < pci_devno; i++) {
 576                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 577                         pdev->ppar = &pci_devs[i];
 578                         break;
 579                 }
 580         }
 581
 582         /* assert downstream PERST# */
 583         if (vendor == PCI_VENDOR_ID_PLX &&
 584             (device & 0xfff0) == 0x8600 &&
 585             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 586                 debug("configuring PLX 860X downstream PERST#\n");
 587                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 588                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 589                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 590
 591                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 592                 dw |= 0xfe;   /* GPIO1-7 output high */
 593                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 594
 595                 mdelay(100);
 596         }
 597 }
 598 #endif /* CONFIG_CMD_PCI */
 599
 600 #ifdef CONFIG_SERIAL_TAG
 601 /*
 602  * called when setting up ATAGS before booting kernel
 603  * populate serialnum from the following (in order of priority):
 604  *   serial# env var
 605  *   eeprom
 606  */
 607 void get_board_serial(struct tag_serialnr *serialnr)
 608 {
 609         char *serial = env_get("serial#");
 610
 611         if (serial) {
 612                 serialnr->high = 0;
 613                 serialnr->low = simple_strtoul(serial, NULL, 10);
 614         } else if (ventana_info.model[0]) {
 615                 serialnr->high = 0;
 616                 serialnr->low = ventana_info.serial;
 617         } else {
 618                 serialnr->high = 0;
 619                 serialnr->low = 0;
 620         }
 621 }
 622 #endif
 623
 624 /*
 625  * Board Support
 626  */
 627
 628 int board_early_init_f(void)
 629 {
 630         setup_iomux_uart();
 631
 632 #if defined(CONFIG_VIDEO_IPUV3)
 633         setup_display();
 634 #endif
 635         return 0;
 636 }
 637
 638 int dram_init(void)
 639 {
 640         gd->ram_size = imx_ddr_size();
 641         return 0;
 642 }
 643
 644 int board_init(void)
 645 {
 646         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 647
 648         clrsetbits_le32(&iomuxc_regs->gpr[1],
 649                         IOMUXC_GPR1_OTG_ID_MASK,
 650                         IOMUXC_GPR1_OTG_ID_GPIO1);
 651
 652         /* address of linux boot parameters */
 653         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 654
 655         /* read Gateworks EEPROM into global struct (used later) */
 656         setup_ventana_i2c(0);
 657         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 658
 659 #ifdef CONFIG_CMD_NAND
 660         if (gpio_cfg[board_type].nand)
 661                 setup_gpmi_nand();
 662 #endif
 663 #ifdef CONFIG_MXC_SPI
 664         setup_spi();
 665 #endif
 666         setup_ventana_i2c(1);
 667         setup_ventana_i2c(2);
 668
 669 #ifdef CONFIG_SATA
 670         setup_sata();
 671 #endif
 672
 673         setup_iomux_gpio(board_type, &ventana_info);
 674
 675         return 0;
 676 }
 677
 678 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 679 /*
 680  * called during late init (after relocation and after board_init())
 681  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 682  * EEPROM read.
 683  */
 684 int checkboard(void)
 685 {
 686         struct ventana_board_info *info = &ventana_info;
 687         unsigned char buf[4];
 688         const char *p;
 689         int quiet; /* Quiet or minimal output mode */
 690
 691         quiet = 0;
 692         p = env_get("quiet");
 693         if (p)
 694                 quiet = simple_strtol(p, NULL, 10);
 695         else
 696                 env_set("quiet", "0");
 697
 698         puts("\nGateworks Corporation Copyright 2014\n");
 699         if (info->model[0]) {
 700                 printf("Model: %s\n", info->model);
 701                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 702                        info->mfgdate[0], info->mfgdate[1],
 703                        info->mfgdate[2], info->mfgdate[3]);
 704                 printf("Serial:%d\n", info->serial);
 705         } else {
 706                 puts("Invalid EEPROM - board will not function fully\n");
 707         }
 708         if (quiet)
 709                 return 0;
 710
 711         /* Display GSC firmware revision/CRC/status */
 712         gsc_info(0);
 713
 714         /* Display RTC */
 715         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 716                 printf("RTC:   %d\n",
 717                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 718         }
 719
 720         return 0;
 721 }
 722 #endif
 723
 724 #ifdef CONFIG_CMD_BMODE
 725 /*
 726  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 727  * see Table 8-11 and Table 5-9
 728  *  BOOT_CFG1[7] = 1 (boot from NAND)
 729  *  BOOT_CFG1[5] = 0 - raw NAND
 730  *  BOOT_CFG1[4] = 0 - default pad settings
 731  *  BOOT_CFG1[3:2] = 00 - devices = 1
 732  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 733  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 734  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 735  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 736  */
 737 static const struct boot_mode board_boot_modes[] = {
 738         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 739         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 740         { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
 741         { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
 742         { NULL, 0 },
 743 };
 744 #endif
 745
 746 /* late init */
 747 int misc_init_r(void)
 748 {
 749         struct ventana_board_info *info = &ventana_info;
 750         char buf[256];
 751         int i;
 752
 753         /* set env vars based on EEPROM data */
 754         if (ventana_info.model[0]) {
 755                 char str[16], fdt[36];
 756                 char *p;
 757                 const char *cputype = "";
 758
 759                 /*
 760                  * FDT name will be prefixed with CPU type.  Three versions
 761                  * will be created each increasingly generic and bootloader
 762                  * env scripts will try loading each from most specific to
 763                  * least.
 764                  */
 765                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 766                     is_cpu_type(MXC_CPU_MX6D))
 767                         cputype = "imx6q";
 768                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 769                          is_cpu_type(MXC_CPU_MX6SOLO))
 770                         cputype = "imx6dl";
 771                 env_set("soctype", cputype);
 772                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 773                         env_set("flash_layout", "large");
 774                 else
 775                         env_set("flash_layout", "normal");
 776                 memset(str, 0, sizeof(str));
 777                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 778                         str[i] = tolower(info->model[i]);
 779                 env_set("model", str);
 780                 if (!env_get("fdt_file")) {
 781                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 782                         env_set("fdt_file", fdt);
 783                 }
 784                 p = strchr(str, '-');
 785                 if (p) {
 786                         *p++ = 0;
 787
 788                         env_set("model_base", str);
 789                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 790                         env_set("fdt_file1", fdt);
 791                         if (board_type != GW551x &&
 792                             board_type != GW552x &&
 793                             board_type != GW553x &&
 794                             board_type != GW560x)
 795                                 str[4] = 'x';
 796                         str[5] = 'x';
 797                         str[6] = 0;
 798                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 799                         env_set("fdt_file2", fdt);
 800                 }
 801
 802                 /* initialize env from EEPROM */
 803                 if (test_bit(EECONFIG_ETH0, info->config) &&
 804                     !env_get("ethaddr")) {
 805                         eth_env_set_enetaddr("ethaddr", info->mac0);
 806                 }
 807                 if (test_bit(EECONFIG_ETH1, info->config) &&
 808                     !env_get("eth1addr")) {
 809                         eth_env_set_enetaddr("eth1addr", info->mac1);
 810                 }
 811
 812                 /* board serial-number */
 813                 sprintf(str, "%6d", info->serial);
 814                 env_set("serial#", str);
 815
 816                 /* memory MB */
 817                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 818                 env_set("mem_mb", str);
 819         }
 820
 821         /* Set a non-initialized hwconfig based on board configuration */
 822         if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
 823                 buf[0] = 0;
 824                 if (gpio_cfg[board_type].rs232_en)
 825                         strcat(buf, "rs232;");
 826                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 827                         char buf1[32];
 828                         sprintf(buf1, "dio%d:mode=gpio;", i);
 829                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 830                                 strcat(buf, buf1);
 831                 }
 832                 env_set("hwconfig", buf);
 833         }
 834
 835         /* setup baseboard specific GPIO based on board and env */
 836         setup_board_gpio(board_type, info);
 837
 838 #ifdef CONFIG_CMD_BMODE
 839         add_board_boot_modes(board_boot_modes);
 840 #endif
 841
 842         /* disable boot watchdog */
 843         gsc_boot_wd_disable();
 844
 845         return 0;
 846 }
 847
 848 #ifdef CONFIG_OF_BOARD_SETUP
 849
 850 static int ft_sethdmiinfmt(void *blob, char *mode)
 851 {
 852         int off;
 853
 854         if (!mode)
 855                 return -EINVAL;
 856
 857         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 858         if (off < 0)
 859                 return off;
 860
 861         if (0 == strcasecmp(mode, "yuv422bt656")) {
 862                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 863                              0x00, 0x00, 0x00 };
 864                 mode = "422_ccir";
 865                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 866                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 867                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 868                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 869                 printf("   set HDMI input mode to %s\n", mode);
 870         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 871                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 872                              0x82, 0x81, 0x00 };
 873                 mode = "422_smp";
 874                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 875                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 876                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 877                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 878                 printf("   set HDMI input mode to %s\n", mode);
 879         } else {
 880                 return -EINVAL;
 881         }
 882
 883         return 0;
 884 }
 885
 886 #if defined(CONFIG_CMD_PCI)
 887 #define PCI_ID(x) ( \
 888         (PCI_BUS(x->devfn)<<16)| \
 889         (PCI_DEV(x->devfn)<<11)| \
 890         (PCI_FUNC(x->devfn)<<8) \
 891         )
 892 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 893 {
 894         uint32_t reg[5];
 895         char node[32];
 896         int np;
 897
 898         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 899                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 900
 901         np = fdt_subnode_offset(blob, par, node);
 902         if (np >= 0)
 903                 return np;
 904         np = fdt_add_subnode(blob, par, node);
 905         if (np < 0) {
 906                 printf("   %s failed: no space\n", __func__);
 907                 return np;
 908         }
 909
 910         memset(reg, 0, sizeof(reg));
 911         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 912         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 913
 914         return np;
 915 }
 916
 917 /* build a path of nested PCI devs for all bridges passed through */
 918 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 919 {
 920         struct pci_dev *bridges[MAX_PCI_DEVS];
 921         int k, np;
 922
 923         /* build list of parents */
 924         np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
 925         if (np < 0)
 926                 return np;
 927
 928         k = 0;
 929         while (dev) {
 930                 bridges[k++] = dev;
 931                 dev = dev->ppar;
 932         };
 933
 934         /* now add them the to DT in reverse order */
 935         while (k--) {
 936                 np = fdt_add_pci_node(blob, np, bridges[k]);
 937                 if (np < 0)
 938                         break;
 939         }
 940
 941         return np;
 942 }
 943
 944 /*
 945  * The GW16082 has a hardware errata errata such that it's
 946  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 947  * of this normal PCI interrupt swizzling will not work so we will
 948  * provide an irq-map via device-tree.
 949  */
 950 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 951 {
 952         int len;
 953         int host;
 954         uint32_t imap_new[8*4*4];
 955         const uint32_t *imap;
 956         uint32_t irq[4];
 957         uint32_t reg[4];
 958         int i;
 959
 960         /* build irq-map based on host controllers map */
 961         host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
 962         if (host < 0) {
 963                 printf("   %s failed: missing host\n", __func__);
 964                 return host;
 965         }
 966
 967         /* use interrupt data from root complex's node */
 968         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 969         if (!imap || len != 128) {
 970                 printf("   %s failed: invalid interrupt-map\n",
 971                        __func__);
 972                 return -FDT_ERR_NOTFOUND;
 973         }
 974
 975         /* obtain irq's of host controller in pin order */
 976         for (i = 0; i < 4; i++)
 977                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 978
 979         /*
 980          * determine number of swizzles necessary:
 981          *   For each bridge we pass through we need to swizzle
 982          *   the number of the slot we are on.
 983          */
 984         struct pci_dev *d;
 985         int b;
 986         b = 0;
 987         d = dev->ppar;
 988         while(d && d->ppar) {
 989                 b += PCI_DEV(d->devfn);
 990                 d = d->ppar;
 991         }
 992
 993         /* create new irq mappings for slots12-15
 994          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
 995          * J3    AD28    12     INTD      INTA
 996          * J4    AD29    13     INTC      INTD
 997          * J5    AD30    14     INTB      INTC
 998          * J2    AD31    15     INTA      INTB
 999          */
1000         for (i = 0; i < 4; i++) {
1001                 /* addr matches bus:dev:func */
1002                 u32 addr = dev->busno << 16 | (12+i) << 11;
1003
1004                 /* default cells from root complex */
1005                 memcpy(&imap_new[i*32], imap, 128);
1006                 /* first cell is PCI device address (BDF) */
1007                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1008                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1009                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1010                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1011                 /* third cell is pin */
1012                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1013                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1014                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1015                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1016                 /* sixth cell is relative interrupt */
1017                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1018                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1019                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1020                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1021         }
1022         fdt_setprop(blob, np, "interrupt-map", imap_new,
1023                     sizeof(imap_new));
1024         reg[0] = cpu_to_fdt32(0xfff00);
1025         reg[1] = 0;
1026         reg[2] = 0;
1027         reg[3] = cpu_to_fdt32(0x7);
1028         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1029         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1030         fdt_setprop_string(blob, np, "device_type", "pci");
1031         fdt_setprop_cell(blob, np, "#address-cells", 3);
1032         fdt_setprop_cell(blob, np, "#size-cells", 2);
1033         printf("   Added custom interrupt-map for GW16082\n");
1034
1035         return 0;
1036 }
1037
1038 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1039 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1040 {
1041         char *tmp, *end;
1042         char mac[16];
1043         unsigned char mac_addr[6];
1044         int j;
1045
1046         sprintf(mac, "eth1addr");
1047         tmp = env_get(mac);
1048         if (tmp) {
1049                 for (j = 0; j < 6; j++) {
1050                         mac_addr[j] = tmp ?
1051                                       simple_strtoul(tmp, &end,16) : 0;
1052                         if (tmp)
1053                                 tmp = (*end) ? end+1 : end;
1054                 }
1055                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1056                             sizeof(mac_addr));
1057                 printf("   Added mac addr for eth1\n");
1058                 return 0;
1059         }
1060
1061         return -1;
1062 }
1063
1064 /*
1065  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1066  * we will walk the PCI bus and add bridge nodes up to the device receiving
1067  * the fixup.
1068  */
1069 void ft_board_pci_fixup(void *blob, bd_t *bd)
1070 {
1071         int i, np;
1072         struct pci_dev *dev;
1073
1074         for (i = 0; i < pci_devno; i++) {
1075                 dev = &pci_devs[i];
1076
1077                 /*
1078                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1079                  * an EEPROM at i2c1-0x50.
1080                  */
1081                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1082                     (dev->device == 0x8240) &&
1083                     (i2c_set_bus_num(1) == 0) &&
1084                     (i2c_probe(0x50) == 0))
1085                 {
1086                         np = fdt_add_pci_path(blob, dev);
1087                         if (np > 0)
1088                                 fdt_fixup_gw16082(blob, np, dev);
1089                 }
1090
1091                 /* ethernet1 mac address */
1092                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1093                          (dev->device == 0x4380))
1094                 {
1095                         np = fdt_add_pci_path(blob, dev);
1096                         if (np > 0)
1097                                 fdt_fixup_sky2(blob, np, dev);
1098                 }
1099         }
1100 }
1101 #endif /* if defined(CONFIG_CMD_PCI) */
1102
1103 void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1104 {
1105         int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1106
1107         if (off) {
1108                 fdt_delprop(blob, off, "ext-reset-output");
1109                 fdt_delprop(blob, off, "fsl,ext-reset-output");
1110         }
1111 }
1112
1113 /*
1114  * called prior to booting kernel or by 'fdt boardsetup' command
1115  *
1116  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1117  *  - mtd partitions based on mtdparts/mtdids env
1118  *  - system-serial (board serial num from EEPROM)
1119  *  - board (full model from EEPROM)
1120  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1121  */
1122 #define WDOG1_ADDR      0x20bc000
1123 #define WDOG2_ADDR      0x20c0000
1124 #define GPIO3_ADDR      0x20a4000
1125 #define USDHC3_ADDR     0x2198000
1126 #define PWM0_ADDR       0x2080000
1127 int ft_board_setup(void *blob, bd_t *bd)
1128 {
1129         struct ventana_board_info *info = &ventana_info;
1130         struct ventana_eeprom_config *cfg;
1131         static const struct node_info nodes[] = {
1132                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1133                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1134         };
1135         const char *model = env_get("model");
1136         const char *display = env_get("display");
1137         int i;
1138         char rev = 0;
1139
1140         /* determine board revision */
1141         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1142                 if (ventana_info.model[i] >= 'A') {
1143                         rev = ventana_info.model[i];
1144                         break;
1145                 }
1146         }
1147
1148         if (env_get("fdt_noauto")) {
1149                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1150                 return 0;
1151         }
1152
1153         if (test_bit(EECONFIG_NAND, info->config)) {
1154                 /* Update partition nodes using info from mtdparts env var */
1155                 puts("   Updating MTD partitions...\n");
1156                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1157         }
1158
1159         /* Update display timings from display env var */
1160         if (display) {
1161                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1162                                       display) >= 0)
1163                         printf("   Set display timings for %s...\n", display);
1164         }
1165
1166         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1167
1168         /* board serial number */
1169         fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1170                     strlen(env_get("serial#")) + 1);
1171
1172         /* board (model contains model from device-tree) */
1173         fdt_setprop(blob, 0, "board", info->model,
1174                     strlen((const char *)info->model) + 1);
1175
1176         /* set desired digital video capture format */
1177         ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1178
1179         /*
1180          * Board model specific fixups
1181          */
1182         switch (board_type) {
1183         case GW51xx:
1184                 /*
1185                  * disable wdog node for GW51xx-A/B to work around
1186                  * errata causing wdog timer to be unreliable.
1187                  */
1188                 if (rev >= 'A' && rev < 'C') {
1189                         i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1190                                                           WDOG1_ADDR);
1191                         if (i)
1192                                 fdt_status_disabled(blob, i);
1193                 }
1194
1195                 /* GW51xx-E adds WDOG1_B external reset */
1196                 if (rev < 'E')
1197                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1198                 break;
1199
1200         case GW52xx:
1201                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1202                 if (info->model[4] == '2') {
1203                         u32 handle = 0;
1204                         u32 *range = NULL;
1205
1206                         i = fdt_node_offset_by_compatible(blob, -1,
1207                                                           "fsl,imx6q-pcie");
1208                         if (i)
1209                                 range = (u32 *)fdt_getprop(blob, i,
1210                                                            "reset-gpio", NULL);
1211
1212                         if (range) {
1213                                 i = fdt_node_offset_by_compat_reg(blob,
1214                                         "fsl,imx6q-gpio", GPIO3_ADDR);
1215                                 if (i)
1216                                         handle = fdt_get_phandle(blob, i);
1217                                 if (handle) {
1218                                         range[0] = cpu_to_fdt32(handle);
1219                                         range[1] = cpu_to_fdt32(23);
1220                                 }
1221                         }
1222
1223                         /* these have broken usd_vsel */
1224                         if (strstr((const char *)info->model, "SP318-B") ||
1225                             strstr((const char *)info->model, "SP331-B"))
1226                                 gpio_cfg[board_type].usd_vsel = 0;
1227
1228                         /* GW522x-B adds WDOG1_B external reset */
1229                         if (rev < 'B')
1230                                 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1231                 }
1232
1233                 /* GW520x-E adds WDOG1_B external reset */
1234                 else if (info->model[4] == '0' && rev < 'E')
1235                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1236                 break;
1237
1238         case GW53xx:
1239                 /* GW53xx-E adds WDOG1_B external reset */
1240                 if (rev < 'E')
1241                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1242                 break;
1243
1244         case GW54xx:
1245                 /*
1246                  * disable serial2 node for GW54xx for compatibility with older
1247                  * 3.10.x kernel that improperly had this node enabled in the DT
1248                  */
1249                 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1250                                         0);
1251
1252                 /* GW54xx-E adds WDOG2_B external reset */
1253                 if (rev < 'E')
1254                         ft_board_wdog_fixup(blob, WDOG2_ADDR);
1255                 break;
1256
1257         case GW551x:
1258                 /*
1259                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1260                  * causing non functional digital video in (it is not hooked up)
1261                  */
1262                 if (rev == 'A') {
1263                         u32 *range = NULL;
1264                         int len;
1265                         const u32 *handle = NULL;
1266
1267                         i = fdt_node_offset_by_compatible(blob, -1,
1268                                                 "fsl,imx-tda1997x-video");
1269                         if (i)
1270                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1271                                                      NULL);
1272                         if (handle)
1273                                 i = fdt_node_offset_by_phandle(blob,
1274                                                         fdt32_to_cpu(*handle));
1275                         if (i)
1276                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1277                                                            &len);
1278                         if (range) {
1279                                 len /= sizeof(u32);
1280                                 for (i = 0; i < len; i += 6) {
1281                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1282                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1283                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1284                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1285                                             mux_reg == 0x260 &&
1286                                             conf_reg == 0x630)
1287                                                 range[i+3] = cpu_to_fdt32(0x5);
1288                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1289                                                  mux_reg == 0x08c &&
1290                                                  conf_reg == 0x3a0)
1291                                                 range[i+3] = cpu_to_fdt32(0x5);
1292                                 }
1293                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1294                                                     len);
1295                         }
1296
1297                         /* set BT656 video format */
1298                         ft_sethdmiinfmt(blob, "yuv422bt656");
1299                 }
1300
1301                 /* GW551x-C adds WDOG1_B external reset */
1302                 if (rev < 'C')
1303                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1304                 break;
1305         case GW5901:
1306         case GW5902:
1307                 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1308                 if (rev < 'B')
1309                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1310                 break;
1311         }
1312
1313         /* Configure DIO */
1314         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1315                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1316                 char arg[10];
1317
1318                 sprintf(arg, "dio%d", i);
1319                 if (!hwconfig(arg))
1320                         continue;
1321                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1322                 {
1323                         phys_addr_t addr;
1324                         int off;
1325
1326                         printf("   Enabling pwm%d for DIO%d\n",
1327                                cfg->pwm_param, i);
1328                         addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1329                         off = fdt_node_offset_by_compat_reg(blob,
1330                                                             "fsl,imx6q-pwm",
1331                                                             addr);
1332                         if (off)
1333                                 fdt_status_okay(blob, off);
1334                 }
1335         }
1336
1337         /* remove no-1-8-v if UHS-I support is present */
1338         if (gpio_cfg[board_type].usd_vsel) {
1339                 debug("Enabling UHS-I support\n");
1340                 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1341                                                   USDHC3_ADDR);
1342                 if (i)
1343                         fdt_delprop(blob, i, "no-1-8-v");
1344         }
1345
1346 #if defined(CONFIG_CMD_PCI)
1347         if (!env_get("nopcifixup"))
1348                 ft_board_pci_fixup(blob, bd);
1349 #endif
1350
1351         /*
1352          * Peripheral Config:
1353          *  remove nodes by alias path if EEPROM config tells us the
1354          *  peripheral is not loaded on the board.
1355          */
1356         if (env_get("fdt_noconfig")) {
1357                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1358                 return 0;
1359         }
1360         cfg = econfig;
1361         while (cfg->name) {
1362                 if (!test_bit(cfg->bit, info->config)) {
1363                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1364                                                cfg->dtalias : cfg->name);
1365                 }
1366                 cfg++;
1367         }
1368
1369         return 0;
1370 }
1371 #endif /* CONFIG_OF_BOARD_SETUP */
1372
1373 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1374         .reg = (struct mxc_uart *)UART2_BASE,
1375 };
1376
1377 U_BOOT_DEVICE(ventana_serial) = {
1378         .name   = "serial_mxc",
1379         .platdata = &ventana_mxc_serial_plat,
1380 };