1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Gateworks Corporation
5 * Author: Tim Harvey <tharvey@gateworks.com>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/sata.h>
19 #include <asm/mach-imx/spi.h>
20 #include <asm/mach-imx/video.h>
22 #include <asm/setup.h>
24 #include <dm/platform_data/serial_mxc.h>
28 #include <fdt_support.h>
29 #include <fsl_esdhc_imx.h>
30 #include <jffs2/load_kernel.h>
31 #include <linux/ctype.h>
36 #include <power/pmic.h>
37 #include <power/ltc3676_pmic.h>
38 #include <power/pfuze100_pmic.h>
39 #include <fdt_support.h>
40 #include <jffs2/load_kernel.h>
41 #include <spi_flash.h>
46 DECLARE_GLOBAL_DATA_PTR;
50 * EEPROM board info struct populated by read_eeprom so that we only have to
53 struct ventana_board_info ventana_info;
55 static int board_type;
58 static iomux_v3_cfg_t const enet_pads[] = {
59 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
60 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
61 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
62 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
63 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
64 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
65 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
66 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
67 MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
69 MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
76 MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
81 #ifdef CONFIG_CMD_NAND
82 static iomux_v3_cfg_t const nfc_pads[] = {
83 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
84 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
85 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
86 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
87 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
89 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
90 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 static void setup_gpmi_nand(void)
102 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
104 /* config gpmi nand iomux */
105 SETUP_IOMUX_PADS(nfc_pads);
107 /* config gpmi and bch clock to 100 MHz */
108 clrsetbits_le32(&mxc_ccm->cs2cdr,
109 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
110 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
111 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
112 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
113 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
114 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
116 /* enable gpmi and bch clock gating */
117 setbits_le32(&mxc_ccm->CCGR4,
118 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
119 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
120 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
121 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
122 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
124 /* enable apbh clock gating */
125 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
129 static void setup_iomux_enet(int gpio)
131 SETUP_IOMUX_PADS(enet_pads);
133 /* toggle PHY_RST# */
134 gpio_request(gpio, "phy_rst#");
135 gpio_direction_output(gpio, 0);
137 gpio_set_value(gpio, 1);
141 #ifdef CONFIG_USB_EHCI_MX6
142 static iomux_v3_cfg_t const usb_pads[] = {
143 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
144 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
146 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
149 int board_ehci_hcd_init(int port)
153 SETUP_IOMUX_PADS(usb_pads);
156 switch (board_type) {
160 gpio = (IMX_GPIO_NR(1, 9));
164 gpio = (IMX_GPIO_NR(1, 16));
170 /* request and toggle hub rst */
171 gpio_request(gpio, "usb_hub_rst#");
172 gpio_direction_output(gpio, 0);
174 gpio_set_value(gpio, 1);
179 int board_ehci_power(int port, int on)
181 /* enable OTG VBUS */
182 if (!port && board_type < GW_UNKNOWN) {
183 if (gpio_cfg[board_type].otgpwr_en)
184 gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
188 #endif /* CONFIG_USB_EHCI_MX6 */
190 #ifdef CONFIG_MXC_SPI
191 iomux_v3_cfg_t const ecspi1_pads[] = {
193 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
194 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
195 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
196 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
199 int board_spi_cs_gpio(unsigned bus, unsigned cs)
201 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
204 static void setup_spi(void)
206 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
207 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
208 SETUP_IOMUX_PADS(ecspi1_pads);
212 /* configure eth0 PHY board-specific LED behavior */
213 int board_phy_config(struct phy_device *phydev)
218 if (phydev->phy_id == 0x1410dd1) {
220 * Page 3, Register 16: LED[2:0] Function Control Register
221 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
222 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
224 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
225 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
228 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
229 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
233 else if (phydev->phy_id == 0x2000a231) {
234 /* configure register 0x170 for ref CLKOUT */
235 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
236 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
237 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
238 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
240 val |= 0x0b00; /* chD tx clock*/
241 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
244 if (phydev->drv->config)
245 phydev->drv->config(phydev);
250 #ifdef CONFIG_MV88E61XX_SWITCH
251 int mv88e61xx_hw_reset(struct phy_device *phydev)
253 struct mii_dev *bus = phydev->bus;
255 /* GPIO[0] output, CLK125 */
256 debug("enabling RGMII_REFCLK\n");
257 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
258 0x1a /*MV_SCRATCH_MISC*/,
259 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
260 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
261 0x1a /*MV_SCRATCH_MISC*/,
262 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
264 /* RGMII delay - Physical Control register bit[15:14] */
265 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
266 /* forced 1000mbps full-duplex link */
267 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
268 phydev->autoneg = AUTONEG_DISABLE;
269 phydev->speed = SPEED_1000;
270 phydev->duplex = DUPLEX_FULL;
272 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
273 bus->write(bus, 0x10, 0, 0x16, 0x8088);
274 bus->write(bus, 0x11, 0, 0x16, 0x8088);
275 bus->write(bus, 0x12, 0, 0x16, 0x8088);
276 bus->write(bus, 0x13, 0, 0x16, 0x8088);
280 #endif // CONFIG_MV88E61XX_SWITCH
282 int board_eth_init(bd_t *bis)
284 #ifdef CONFIG_FEC_MXC
285 struct ventana_board_info *info = &ventana_info;
287 if (test_bit(EECONFIG_ETH0, info->config)) {
288 setup_iomux_enet(GP_PHY_RST);
294 e1000_initialize(bis);
298 /* For otg ethernet*/
299 usb_eth_initialize(bis);
302 /* default to the first detected enet dev */
303 if (!env_get("ethprime")) {
304 struct eth_device *dev = eth_get_dev_by_index(0);
306 env_set("ethprime", dev->name);
307 printf("set ethprime to %s\n", env_get("ethprime"));
314 #if defined(CONFIG_VIDEO_IPUV3)
316 static void enable_hdmi(struct display_info_t const *dev)
318 imx_enable_hdmi_phy();
321 static int detect_i2c(struct display_info_t const *dev)
323 return i2c_set_bus_num(dev->bus) == 0 &&
324 i2c_probe(dev->addr) == 0;
327 static void enable_lvds(struct display_info_t const *dev)
329 struct iomuxc *iomux = (struct iomuxc *)
332 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
333 u32 reg = readl(&iomux->gpr[2]);
334 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
335 writel(reg, &iomux->gpr[2]);
337 /* Enable Backlight */
338 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
339 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
340 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
341 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
342 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
345 struct display_info_t const displays[] = {{
349 .pixfmt = IPU_PIX_FMT_RGB24,
350 .detect = detect_hdmi,
351 .enable = enable_hdmi,
365 .vmode = FB_VMODE_NONINTERLACED
367 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
370 .pixfmt = IPU_PIX_FMT_LVDS666,
371 .detect = detect_i2c,
372 .enable = enable_lvds,
374 .name = "Hannstar-XGA",
386 .vmode = FB_VMODE_NONINTERLACED
392 .enable = enable_lvds,
393 .pixfmt = IPU_PIX_FMT_LVDS666,
395 .name = "DLC700JMGT4",
397 .xres = 1024, /* 1024x600active pixels */
399 .pixclock = 15385, /* 64MHz */
407 .vmode = FB_VMODE_NONINTERLACED
413 .enable = enable_lvds,
414 .pixfmt = IPU_PIX_FMT_LVDS666,
416 .name = "DLC800FIGT3",
418 .xres = 1024, /* 1024x768 active pixels */
420 .pixclock = 15385, /* 64MHz */
428 .vmode = FB_VMODE_NONINTERLACED
432 .detect = detect_i2c,
433 .enable = enable_lvds,
434 .pixfmt = IPU_PIX_FMT_LVDS666,
440 .pixclock = 15385, /* 64MHz */
448 .vmode = FB_VMODE_NONINTERLACED
452 size_t display_count = ARRAY_SIZE(displays);
454 static void setup_display(void)
456 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
457 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
462 /* Turn on LDB0,IPU,IPU DI0 clocks */
463 reg = __raw_readl(&mxc_ccm->CCGR3);
464 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
465 writel(reg, &mxc_ccm->CCGR3);
467 /* set LDB0, LDB1 clk select to 011/011 */
468 reg = readl(&mxc_ccm->cs2cdr);
469 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
470 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
471 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
472 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
473 writel(reg, &mxc_ccm->cs2cdr);
475 reg = readl(&mxc_ccm->cscmr2);
476 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
477 writel(reg, &mxc_ccm->cscmr2);
479 reg = readl(&mxc_ccm->chsccdr);
480 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
481 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
482 writel(reg, &mxc_ccm->chsccdr);
484 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
485 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
486 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
487 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
488 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
489 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
490 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
491 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
492 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
493 writel(reg, &iomux->gpr[2]);
495 reg = readl(&iomux->gpr[3]);
496 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
497 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
498 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
499 writel(reg, &iomux->gpr[3]);
501 /* LVDS Backlight GPIO on LVDS connector - output low */
502 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
503 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
505 #endif /* CONFIG_VIDEO_IPUV3 */
507 /* setup board specific PMIC */
508 int power_init_board(void)
514 #if defined(CONFIG_CMD_PCI)
515 int imx6_pcie_toggle_reset(void)
517 if (board_type < GW_UNKNOWN) {
518 uint pin = gpio_cfg[board_type].pcie_rst;
519 gpio_request(pin, "pci_rst#");
520 gpio_direction_output(pin, 0);
522 gpio_direction_output(pin, 1);
528 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
529 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
530 * properly and assert reset for 100ms.
532 #define MAX_PCI_DEVS 32
535 unsigned short vendor;
536 unsigned short device;
537 unsigned short class;
538 unsigned short busno; /* subbordinate busno */
539 struct pci_dev *ppar;
541 struct pci_dev pci_devs[MAX_PCI_DEVS];
545 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
546 unsigned short vendor, unsigned short device,
547 unsigned short class)
551 struct pci_dev *pdev = &pci_devs[pci_devno++];
553 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
554 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
556 /* store array of devs for later use in device-tree fixup */
558 pdev->vendor = vendor;
559 pdev->device = device;
562 if (class == PCI_CLASS_BRIDGE_PCI)
563 pdev->busno = ++pci_bridgeno;
567 /* fixup RC - it should be 00:00.0 not 00:01.0 */
568 if (PCI_BUS(dev) == 0)
571 /* find dev's parent */
572 for (i = 0; i < pci_devno; i++) {
573 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
574 pdev->ppar = &pci_devs[i];
579 /* assert downstream PERST# */
580 if (vendor == PCI_VENDOR_ID_PLX &&
581 (device & 0xfff0) == 0x8600 &&
582 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
583 debug("configuring PLX 860X downstream PERST#\n");
584 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
585 dw |= 0xaaa8; /* GPIO1-7 outputs */
586 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
588 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
589 dw |= 0xfe; /* GPIO1-7 output high */
590 pci_hose_write_config_dword(hose, dev, 0x644, dw);
595 #endif /* CONFIG_CMD_PCI */
597 #ifdef CONFIG_SERIAL_TAG
599 * called when setting up ATAGS before booting kernel
600 * populate serialnum from the following (in order of priority):
604 void get_board_serial(struct tag_serialnr *serialnr)
606 char *serial = env_get("serial#");
610 serialnr->low = simple_strtoul(serial, NULL, 10);
611 } else if (ventana_info.model[0]) {
613 serialnr->low = ventana_info.serial;
625 int board_early_init_f(void)
629 #if defined(CONFIG_VIDEO_IPUV3)
637 gd->ram_size = imx_ddr_size();
643 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
645 clrsetbits_le32(&iomuxc_regs->gpr[1],
646 IOMUXC_GPR1_OTG_ID_MASK,
647 IOMUXC_GPR1_OTG_ID_GPIO1);
649 /* address of linux boot parameters */
650 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
652 /* read Gateworks EEPROM into global struct (used later) */
653 setup_ventana_i2c(0);
654 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
656 #ifdef CONFIG_CMD_NAND
657 if (gpio_cfg[board_type].nand)
660 #ifdef CONFIG_MXC_SPI
663 setup_ventana_i2c(1);
664 setup_ventana_i2c(2);
670 setup_iomux_gpio(board_type, &ventana_info);
675 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
677 * called during late init (after relocation and after board_init())
678 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
683 struct ventana_board_info *info = &ventana_info;
684 unsigned char buf[4];
686 int quiet; /* Quiet or minimal output mode */
689 p = env_get("quiet");
691 quiet = simple_strtol(p, NULL, 10);
693 env_set("quiet", "0");
695 puts("\nGateworks Corporation Copyright 2014\n");
696 if (info->model[0]) {
697 printf("Model: %s\n", info->model);
698 printf("MFGDate: %02x-%02x-%02x%02x\n",
699 info->mfgdate[0], info->mfgdate[1],
700 info->mfgdate[2], info->mfgdate[3]);
701 printf("Serial:%d\n", info->serial);
703 puts("Invalid EEPROM - board will not function fully\n");
708 /* Display GSC firmware revision/CRC/status */
712 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
714 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
721 #ifdef CONFIG_CMD_BMODE
723 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
724 * see Table 8-11 and Table 5-9
725 * BOOT_CFG1[7] = 1 (boot from NAND)
726 * BOOT_CFG1[5] = 0 - raw NAND
727 * BOOT_CFG1[4] = 0 - default pad settings
728 * BOOT_CFG1[3:2] = 00 - devices = 1
729 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
730 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
731 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
732 * BOOT_CFG2[0] = 0 - Reset time 12ms
734 static const struct boot_mode board_boot_modes[] = {
735 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
736 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
737 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
738 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
744 int misc_init_r(void)
746 struct ventana_board_info *info = &ventana_info;
750 /* set env vars based on EEPROM data */
751 if (ventana_info.model[0]) {
752 char str[16], fdt[36];
754 const char *cputype = "";
757 * FDT name will be prefixed with CPU type. Three versions
758 * will be created each increasingly generic and bootloader
759 * env scripts will try loading each from most specific to
762 if (is_cpu_type(MXC_CPU_MX6Q) ||
763 is_cpu_type(MXC_CPU_MX6D))
765 else if (is_cpu_type(MXC_CPU_MX6DL) ||
766 is_cpu_type(MXC_CPU_MX6SOLO))
768 env_set("soctype", cputype);
769 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
770 env_set("flash_layout", "large");
772 env_set("flash_layout", "normal");
773 memset(str, 0, sizeof(str));
774 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
775 str[i] = tolower(info->model[i]);
776 env_set("model", str);
777 if (!env_get("fdt_file")) {
778 sprintf(fdt, "%s-%s.dtb", cputype, str);
779 env_set("fdt_file", fdt);
781 p = strchr(str, '-');
785 env_set("model_base", str);
786 sprintf(fdt, "%s-%s.dtb", cputype, str);
787 env_set("fdt_file1", fdt);
788 if (board_type != GW551x &&
789 board_type != GW552x &&
790 board_type != GW553x &&
791 board_type != GW560x)
795 sprintf(fdt, "%s-%s.dtb", cputype, str);
796 env_set("fdt_file2", fdt);
799 /* initialize env from EEPROM */
800 if (test_bit(EECONFIG_ETH0, info->config) &&
801 !env_get("ethaddr")) {
802 eth_env_set_enetaddr("ethaddr", info->mac0);
804 if (test_bit(EECONFIG_ETH1, info->config) &&
805 !env_get("eth1addr")) {
806 eth_env_set_enetaddr("eth1addr", info->mac1);
809 /* board serial-number */
810 sprintf(str, "%6d", info->serial);
811 env_set("serial#", str);
814 sprintf(str, "%d", (int) (gd->ram_size >> 20));
815 env_set("mem_mb", str);
818 /* Set a non-initialized hwconfig based on board configuration */
819 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
821 if (gpio_cfg[board_type].rs232_en)
822 strcat(buf, "rs232;");
823 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
825 sprintf(buf1, "dio%d:mode=gpio;", i);
826 if (strlen(buf) + strlen(buf1) < sizeof(buf))
829 env_set("hwconfig", buf);
832 /* setup baseboard specific GPIO based on board and env */
833 setup_board_gpio(board_type, info);
835 #ifdef CONFIG_CMD_BMODE
836 add_board_boot_modes(board_boot_modes);
839 /* disable boot watchdog */
840 gsc_boot_wd_disable();
845 #ifdef CONFIG_OF_BOARD_SETUP
847 static int ft_sethdmiinfmt(void *blob, char *mode)
854 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
858 if (0 == strcasecmp(mode, "yuv422bt656")) {
859 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
862 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
863 fdt_setprop_u32(blob, off, "vidout_trc", 1);
864 fdt_setprop_u32(blob, off, "vidout_blc", 1);
865 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
866 printf(" set HDMI input mode to %s\n", mode);
867 } else if (0 == strcasecmp(mode, "yuv422smp")) {
868 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
871 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
872 fdt_setprop_u32(blob, off, "vidout_trc", 0);
873 fdt_setprop_u32(blob, off, "vidout_blc", 0);
874 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
875 printf(" set HDMI input mode to %s\n", mode);
883 #if defined(CONFIG_CMD_PCI)
884 #define PCI_ID(x) ( \
885 (PCI_BUS(x->devfn)<<16)| \
886 (PCI_DEV(x->devfn)<<11)| \
887 (PCI_FUNC(x->devfn)<<8) \
889 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
895 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
896 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
898 np = fdt_subnode_offset(blob, par, node);
901 np = fdt_add_subnode(blob, par, node);
903 printf(" %s failed: no space\n", __func__);
907 memset(reg, 0, sizeof(reg));
908 reg[0] = cpu_to_fdt32(PCI_ID(dev));
909 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
914 /* build a path of nested PCI devs for all bridges passed through */
915 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
917 struct pci_dev *bridges[MAX_PCI_DEVS];
920 /* build list of parents */
921 np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
931 /* now add them the to DT in reverse order */
933 np = fdt_add_pci_node(blob, np, bridges[k]);
942 * The GW16082 has a hardware errata errata such that it's
943 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
944 * of this normal PCI interrupt swizzling will not work so we will
945 * provide an irq-map via device-tree.
947 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
951 uint32_t imap_new[8*4*4];
952 const uint32_t *imap;
957 /* build irq-map based on host controllers map */
958 host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
960 printf(" %s failed: missing host\n", __func__);
964 /* use interrupt data from root complex's node */
965 imap = fdt_getprop(blob, host, "interrupt-map", &len);
966 if (!imap || len != 128) {
967 printf(" %s failed: invalid interrupt-map\n",
969 return -FDT_ERR_NOTFOUND;
972 /* obtain irq's of host controller in pin order */
973 for (i = 0; i < 4; i++)
974 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
977 * determine number of swizzles necessary:
978 * For each bridge we pass through we need to swizzle
979 * the number of the slot we are on.
985 while(d && d->ppar) {
986 b += PCI_DEV(d->devfn);
990 /* create new irq mappings for slots12-15
991 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
992 * J3 AD28 12 INTD INTA
993 * J4 AD29 13 INTC INTD
994 * J5 AD30 14 INTB INTC
995 * J2 AD31 15 INTA INTB
997 for (i = 0; i < 4; i++) {
998 /* addr matches bus:dev:func */
999 u32 addr = dev->busno << 16 | (12+i) << 11;
1001 /* default cells from root complex */
1002 memcpy(&imap_new[i*32], imap, 128);
1003 /* first cell is PCI device address (BDF) */
1004 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1005 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1006 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1007 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1008 /* third cell is pin */
1009 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1010 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1011 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1012 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1013 /* sixth cell is relative interrupt */
1014 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1015 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1016 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1017 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1019 fdt_setprop(blob, np, "interrupt-map", imap_new,
1021 reg[0] = cpu_to_fdt32(0xfff00);
1024 reg[3] = cpu_to_fdt32(0x7);
1025 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1026 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1027 fdt_setprop_string(blob, np, "device_type", "pci");
1028 fdt_setprop_cell(blob, np, "#address-cells", 3);
1029 fdt_setprop_cell(blob, np, "#size-cells", 2);
1030 printf(" Added custom interrupt-map for GW16082\n");
1035 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1036 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1040 unsigned char mac_addr[6];
1043 sprintf(mac, "eth1addr");
1046 for (j = 0; j < 6; j++) {
1048 simple_strtoul(tmp, &end,16) : 0;
1050 tmp = (*end) ? end+1 : end;
1052 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1054 printf(" Added mac addr for eth1\n");
1062 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1063 * we will walk the PCI bus and add bridge nodes up to the device receiving
1066 void ft_board_pci_fixup(void *blob, bd_t *bd)
1069 struct pci_dev *dev;
1071 for (i = 0; i < pci_devno; i++) {
1075 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1076 * an EEPROM at i2c1-0x50.
1078 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1079 (dev->device == 0x8240) &&
1080 (i2c_set_bus_num(1) == 0) &&
1081 (i2c_probe(0x50) == 0))
1083 np = fdt_add_pci_path(blob, dev);
1085 fdt_fixup_gw16082(blob, np, dev);
1088 /* ethernet1 mac address */
1089 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1090 (dev->device == 0x4380))
1092 np = fdt_add_pci_path(blob, dev);
1094 fdt_fixup_sky2(blob, np, dev);
1098 #endif /* if defined(CONFIG_CMD_PCI) */
1100 void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1102 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1105 fdt_delprop(blob, off, "ext-reset-output");
1106 fdt_delprop(blob, off, "fsl,ext-reset-output");
1111 * called prior to booting kernel or by 'fdt boardsetup' command
1113 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1114 * - mtd partitions based on mtdparts/mtdids env
1115 * - system-serial (board serial num from EEPROM)
1116 * - board (full model from EEPROM)
1117 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1119 #define WDOG1_ADDR 0x20bc000
1120 #define WDOG2_ADDR 0x20c0000
1121 #define GPIO3_ADDR 0x20a4000
1122 #define USDHC3_ADDR 0x2198000
1123 #define PWM0_ADDR 0x2080000
1124 int ft_board_setup(void *blob, bd_t *bd)
1126 struct ventana_board_info *info = &ventana_info;
1127 struct ventana_eeprom_config *cfg;
1128 static const struct node_info nodes[] = {
1129 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1130 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1132 const char *model = env_get("model");
1133 const char *display = env_get("display");
1137 /* determine board revision */
1138 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1139 if (ventana_info.model[i] >= 'A') {
1140 rev = ventana_info.model[i];
1145 if (env_get("fdt_noauto")) {
1146 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1150 if (test_bit(EECONFIG_NAND, info->config)) {
1151 /* Update partition nodes using info from mtdparts env var */
1152 puts(" Updating MTD partitions...\n");
1153 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1156 /* Update display timings from display env var */
1158 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1160 printf(" Set display timings for %s...\n", display);
1163 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1165 /* board serial number */
1166 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1167 strlen(env_get("serial#")) + 1);
1169 /* board (model contains model from device-tree) */
1170 fdt_setprop(blob, 0, "board", info->model,
1171 strlen((const char *)info->model) + 1);
1173 /* set desired digital video capture format */
1174 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1177 * Board model specific fixups
1179 switch (board_type) {
1182 * disable wdog node for GW51xx-A/B to work around
1183 * errata causing wdog timer to be unreliable.
1185 if (rev >= 'A' && rev < 'C') {
1186 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1189 fdt_status_disabled(blob, i);
1192 /* GW51xx-E adds WDOG1_B external reset */
1194 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1198 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1199 if (info->model[4] == '2') {
1203 i = fdt_node_offset_by_compatible(blob, -1,
1206 range = (u32 *)fdt_getprop(blob, i,
1207 "reset-gpio", NULL);
1210 i = fdt_node_offset_by_compat_reg(blob,
1211 "fsl,imx6q-gpio", GPIO3_ADDR);
1213 handle = fdt_get_phandle(blob, i);
1215 range[0] = cpu_to_fdt32(handle);
1216 range[1] = cpu_to_fdt32(23);
1220 /* these have broken usd_vsel */
1221 if (strstr((const char *)info->model, "SP318-B") ||
1222 strstr((const char *)info->model, "SP331-B"))
1223 gpio_cfg[board_type].usd_vsel = 0;
1225 /* GW522x-B adds WDOG1_B external reset */
1227 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1230 /* GW520x-E adds WDOG1_B external reset */
1231 else if (info->model[4] == '0' && rev < 'E')
1232 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1236 /* GW53xx-E adds WDOG1_B external reset */
1238 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1243 * disable serial2 node for GW54xx for compatibility with older
1244 * 3.10.x kernel that improperly had this node enabled in the DT
1246 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1249 /* GW54xx-E adds WDOG2_B external reset */
1251 ft_board_wdog_fixup(blob, WDOG2_ADDR);
1256 * isolate CSI0_DATA_EN for GW551x-A to work around errata
1257 * causing non functional digital video in (it is not hooked up)
1262 const u32 *handle = NULL;
1264 i = fdt_node_offset_by_compatible(blob, -1,
1265 "fsl,imx-tda1997x-video");
1267 handle = fdt_getprop(blob, i, "pinctrl-0",
1270 i = fdt_node_offset_by_phandle(blob,
1271 fdt32_to_cpu(*handle));
1273 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1277 for (i = 0; i < len; i += 6) {
1278 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1279 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1280 /* mux PAD_CSI0_DATA_EN to GPIO */
1281 if (is_cpu_type(MXC_CPU_MX6Q) &&
1284 range[i+3] = cpu_to_fdt32(0x5);
1285 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1288 range[i+3] = cpu_to_fdt32(0x5);
1290 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1294 /* set BT656 video format */
1295 ft_sethdmiinfmt(blob, "yuv422bt656");
1298 /* GW551x-C adds WDOG1_B external reset */
1300 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1304 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1306 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1311 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1312 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1315 sprintf(arg, "dio%d", i);
1318 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1323 printf(" Enabling pwm%d for DIO%d\n",
1325 addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1326 off = fdt_node_offset_by_compat_reg(blob,
1330 fdt_status_okay(blob, off);
1334 /* remove no-1-8-v if UHS-I support is present */
1335 if (gpio_cfg[board_type].usd_vsel) {
1336 debug("Enabling UHS-I support\n");
1337 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1340 fdt_delprop(blob, i, "no-1-8-v");
1343 #if defined(CONFIG_CMD_PCI)
1344 if (!env_get("nopcifixup"))
1345 ft_board_pci_fixup(blob, bd);
1349 * Peripheral Config:
1350 * remove nodes by alias path if EEPROM config tells us the
1351 * peripheral is not loaded on the board.
1353 if (env_get("fdt_noconfig")) {
1354 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1359 if (!test_bit(cfg->bit, info->config)) {
1360 fdt_del_node_and_alias(blob, cfg->dtalias ?
1361 cfg->dtalias : cfg->name);
1368 #endif /* CONFIG_OF_BOARD_SETUP */
1370 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1371 .reg = (struct mxc_uart *)UART2_BASE,
1374 U_BOOT_DEVICE(ventana_serial) = {
1375 .name = "serial_mxc",
1376 .platdata = &ventana_mxc_serial_plat,