board/gateworks/gw_ventana/gw_ventana.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Gateworks Corporation
   4  *
   5  * Author: Tim Harvey <tharvey@gateworks.com>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <net.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/arch/mxc_hdmi.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/sata.h>
  21 #include <asm/mach-imx/spi.h>
  22 #include <asm/mach-imx/video.h>
  23 #include <asm/io.h>
  24 #include <asm/setup.h>
  25 #include <dm.h>
  26 #include <dm/platform_data/serial_mxc.h>
  27 #include <env.h>
  28 #include <hwconfig.h>
  29 #include <i2c.h>
  30 #include <fdt_support.h>
  31 #include <fsl_esdhc_imx.h>
  32 #include <jffs2/load_kernel.h>
  33 #include <linux/ctype.h>
  34 #include <miiphy.h>
  35 #include <mtd_node.h>
  36 #include <netdev.h>
  37 #include <pci.h>
  38 #include <linux/delay.h>
  39 #include <linux/libfdt.h>
  40 #include <power/pmic.h>
  41 #include <power/ltc3676_pmic.h>
  42 #include <power/pfuze100_pmic.h>
  43 #include <fdt_support.h>
  44 #include <jffs2/load_kernel.h>
  45 #include <spi_flash.h>
  46
  47 #include "gsc.h"
  48 #include "common.h"
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52
  53 /*
  54  * EEPROM board info struct populated by read_eeprom so that we only have to
  55  * read it once.
  56  */
  57 struct ventana_board_info ventana_info;
  58
  59 static int board_type;
  60
  61 /* ENET */
  62 static iomux_v3_cfg_t const enet_pads[] = {
  63         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  71                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  73                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  80                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         /* PHY nRST */
  82         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  83 };
  84
  85 #ifdef CONFIG_CMD_NAND
  86 static iomux_v3_cfg_t const nfc_pads[] = {
  87         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 100         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 101         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 102 };
 103
 104 static void setup_gpmi_nand(void)
 105 {
 106         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 107
 108         /* config gpmi nand iomux */
 109         SETUP_IOMUX_PADS(nfc_pads);
 110
 111         /* config gpmi and bch clock to 100 MHz */
 112         clrsetbits_le32(&mxc_ccm->cs2cdr,
 113                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 114                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 115                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 116                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 117                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 118                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 119
 120         /* enable gpmi and bch clock gating */
 121         setbits_le32(&mxc_ccm->CCGR4,
 122                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 123                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 124                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 125                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 126                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 127
 128         /* enable apbh clock gating */
 129         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 130 }
 131 #endif
 132
 133 static void setup_iomux_enet(int gpio)
 134 {
 135         SETUP_IOMUX_PADS(enet_pads);
 136
 137         /* toggle PHY_RST# */
 138         gpio_request(gpio, "phy_rst#");
 139         gpio_direction_output(gpio, 0);
 140         mdelay(10);
 141         gpio_set_value(gpio, 1);
 142         mdelay(100);
 143 }
 144
 145 #ifdef CONFIG_USB_EHCI_MX6
 146 static iomux_v3_cfg_t const usb_pads[] = {
 147         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 148         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 149         /* OTG PWR */
 150         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 151 };
 152
 153 int board_ehci_hcd_init(int port)
 154 {
 155         int gpio;
 156
 157         SETUP_IOMUX_PADS(usb_pads);
 158
 159         /* Reset USB HUB */
 160         switch (board_type) {
 161         case GW53xx:
 162         case GW552x:
 163         case GW5906:
 164                 gpio = (IMX_GPIO_NR(1, 9));
 165                 break;
 166         case GW54proto:
 167         case GW54xx:
 168                 gpio = (IMX_GPIO_NR(1, 16));
 169                 break;
 170         default:
 171                 return 0;
 172         }
 173
 174         /* request and toggle hub rst */
 175         gpio_request(gpio, "usb_hub_rst#");
 176         gpio_direction_output(gpio, 0);
 177         mdelay(2);
 178         gpio_set_value(gpio, 1);
 179
 180         return 0;
 181 }
 182
 183 int board_ehci_power(int port, int on)
 184 {
 185         /* enable OTG VBUS */
 186         if (!port && board_type < GW_UNKNOWN) {
 187                 if (gpio_cfg[board_type].otgpwr_en)
 188                         gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
 189         }
 190         return 0;
 191 }
 192 #endif /* CONFIG_USB_EHCI_MX6 */
 193
 194 #ifdef CONFIG_MXC_SPI
 195 iomux_v3_cfg_t const ecspi1_pads[] = {
 196         /* SS1 */
 197         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 198         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 199         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 200         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 201 };
 202
 203 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 204 {
 205         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 206 }
 207
 208 static void setup_spi(void)
 209 {
 210         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 211         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 212         SETUP_IOMUX_PADS(ecspi1_pads);
 213 }
 214 #endif
 215
 216 /* configure eth0 PHY board-specific LED behavior */
 217 int board_phy_config(struct phy_device *phydev)
 218 {
 219         unsigned short val;
 220
 221         /* Marvel 88E1510 */
 222         if (phydev->phy_id == 0x1410dd1) {
 223                 /*
 224                  * Page 3, Register 16: LED[2:0] Function Control Register
 225                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 226                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 227                  */
 228                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 229                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 230                 val &= 0xff00;
 231                 val |= 0x0017;
 232                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 233                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 234         }
 235
 236         /* TI DP83867 */
 237         else if (phydev->phy_id == 0x2000a231) {
 238                 /* configure register 0x170 for ref CLKOUT */
 239                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
 240                 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
 241                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
 242                 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
 243                 val &= ~0x1f00;
 244                 val |= 0x0b00; /* chD tx clock*/
 245                 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
 246         }
 247
 248         if (phydev->drv->config)
 249                 phydev->drv->config(phydev);
 250
 251         return 0;
 252 }
 253
 254 #ifdef CONFIG_MV88E61XX_SWITCH
 255 int mv88e61xx_hw_reset(struct phy_device *phydev)
 256 {
 257         struct mii_dev *bus = phydev->bus;
 258
 259         /* GPIO[0] output, CLK125 */
 260         debug("enabling RGMII_REFCLK\n");
 261         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 262                    0x1a /*MV_SCRATCH_MISC*/,
 263                    (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
 264         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 265                    0x1a /*MV_SCRATCH_MISC*/,
 266                    (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
 267
 268         /* RGMII delay - Physical Control register bit[15:14] */
 269         debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
 270         /* forced 1000mbps full-duplex link */
 271         bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
 272         phydev->autoneg = AUTONEG_DISABLE;
 273         phydev->speed = SPEED_1000;
 274         phydev->duplex = DUPLEX_FULL;
 275
 276         /* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
 277         bus->write(bus, 0x10, 0, 0x16, 0x8088);
 278         bus->write(bus, 0x11, 0, 0x16, 0x8088);
 279         bus->write(bus, 0x12, 0, 0x16, 0x8088);
 280         bus->write(bus, 0x13, 0, 0x16, 0x8088);
 281
 282         return 0;
 283 }
 284 #endif // CONFIG_MV88E61XX_SWITCH
 285
 286 int board_eth_init(bd_t *bis)
 287 {
 288 #ifdef CONFIG_FEC_MXC
 289         struct ventana_board_info *info = &ventana_info;
 290
 291         if (test_bit(EECONFIG_ETH0, info->config)) {
 292                 setup_iomux_enet(GP_PHY_RST);
 293                 cpu_eth_init(bis);
 294         }
 295 #endif
 296
 297 #ifdef CONFIG_E1000
 298         e1000_initialize(bis);
 299 #endif
 300
 301 #ifdef CONFIG_CI_UDC
 302         /* For otg ethernet*/
 303         usb_eth_initialize(bis);
 304 #endif
 305
 306         /* default to the first detected enet dev */
 307         if (!env_get("ethprime")) {
 308                 struct eth_device *dev = eth_get_dev_by_index(0);
 309                 if (dev) {
 310                         env_set("ethprime", dev->name);
 311                         printf("set ethprime to %s\n", env_get("ethprime"));
 312                 }
 313         }
 314
 315         return 0;
 316 }
 317
 318 #if defined(CONFIG_VIDEO_IPUV3)
 319
 320 static void enable_hdmi(struct display_info_t const *dev)
 321 {
 322         imx_enable_hdmi_phy();
 323 }
 324
 325 static int detect_i2c(struct display_info_t const *dev)
 326 {
 327         return i2c_set_bus_num(dev->bus) == 0 &&
 328                 i2c_probe(dev->addr) == 0;
 329 }
 330
 331 static void enable_lvds(struct display_info_t const *dev)
 332 {
 333         struct iomuxc *iomux = (struct iomuxc *)
 334                                 IOMUXC_BASE_ADDR;
 335
 336         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 337         u32 reg = readl(&iomux->gpr[2]);
 338         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 339         writel(reg, &iomux->gpr[2]);
 340
 341         /* Enable Backlight */
 342         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 343         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 344         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 345         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 346         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 347 }
 348
 349 struct display_info_t const displays[] = {{
 350         /* HDMI Output */
 351         .bus    = -1,
 352         .addr   = 0,
 353         .pixfmt = IPU_PIX_FMT_RGB24,
 354         .detect = detect_hdmi,
 355         .enable = enable_hdmi,
 356         .mode   = {
 357                 .name           = "HDMI",
 358                 .refresh        = 60,
 359                 .xres           = 1024,
 360                 .yres           = 768,
 361                 .pixclock       = 15385,
 362                 .left_margin    = 220,
 363                 .right_margin   = 40,
 364                 .upper_margin   = 21,
 365                 .lower_margin   = 7,
 366                 .hsync_len      = 60,
 367                 .vsync_len      = 10,
 368                 .sync           = FB_SYNC_EXT,
 369                 .vmode          = FB_VMODE_NONINTERLACED
 370 } }, {
 371         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 372         .bus    = 2,
 373         .addr   = 0x4,
 374         .pixfmt = IPU_PIX_FMT_LVDS666,
 375         .detect = detect_i2c,
 376         .enable = enable_lvds,
 377         .mode   = {
 378                 .name           = "Hannstar-XGA",
 379                 .refresh        = 60,
 380                 .xres           = 1024,
 381                 .yres           = 768,
 382                 .pixclock       = 15385,
 383                 .left_margin    = 220,
 384                 .right_margin   = 40,
 385                 .upper_margin   = 21,
 386                 .lower_margin   = 7,
 387                 .hsync_len      = 60,
 388                 .vsync_len      = 10,
 389                 .sync           = FB_SYNC_EXT,
 390                 .vmode          = FB_VMODE_NONINTERLACED
 391 } }, {
 392         /* DLC700JMG-T-4 */
 393         .bus    = 2,
 394         .addr   = 0x38,
 395         .detect = NULL,
 396         .enable = enable_lvds,
 397         .pixfmt = IPU_PIX_FMT_LVDS666,
 398         .mode   = {
 399                 .name           = "DLC700JMGT4",
 400                 .refresh        = 60,
 401                 .xres           = 1024,         /* 1024x600active pixels */
 402                 .yres           = 600,
 403                 .pixclock       = 15385,        /* 64MHz */
 404                 .left_margin    = 220,
 405                 .right_margin   = 40,
 406                 .upper_margin   = 21,
 407                 .lower_margin   = 7,
 408                 .hsync_len      = 60,
 409                 .vsync_len      = 10,
 410                 .sync           = FB_SYNC_EXT,
 411                 .vmode          = FB_VMODE_NONINTERLACED
 412 } }, {
 413         /* DLC800FIG-T-3 */
 414         .bus    = 2,
 415         .addr   = 0x14,
 416         .detect = NULL,
 417         .enable = enable_lvds,
 418         .pixfmt = IPU_PIX_FMT_LVDS666,
 419         .mode   = {
 420                 .name           = "DLC800FIGT3",
 421                 .refresh        = 60,
 422                 .xres           = 1024,         /* 1024x768 active pixels */
 423                 .yres           = 768,
 424                 .pixclock       = 15385,        /* 64MHz */
 425                 .left_margin    = 220,
 426                 .right_margin   = 40,
 427                 .upper_margin   = 21,
 428                 .lower_margin   = 7,
 429                 .hsync_len      = 60,
 430                 .vsync_len      = 10,
 431                 .sync           = FB_SYNC_EXT,
 432                 .vmode          = FB_VMODE_NONINTERLACED
 433 } }, {
 434         .bus    = 2,
 435         .addr   = 0x5d,
 436         .detect = detect_i2c,
 437         .enable = enable_lvds,
 438         .pixfmt = IPU_PIX_FMT_LVDS666,
 439         .mode   = {
 440                 .name           = "Z101WX01",
 441                 .refresh        = 60,
 442                 .xres           = 1280,
 443                 .yres           = 800,
 444                 .pixclock       = 15385,        /* 64MHz */
 445                 .left_margin    = 220,
 446                 .right_margin   = 40,
 447                 .upper_margin   = 21,
 448                 .lower_margin   = 7,
 449                 .hsync_len      = 60,
 450                 .vsync_len      = 10,
 451                 .sync           = FB_SYNC_EXT,
 452                 .vmode          = FB_VMODE_NONINTERLACED
 453         }
 454 },
 455 };
 456 size_t display_count = ARRAY_SIZE(displays);
 457
 458 static void setup_display(void)
 459 {
 460         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 461         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 462         int reg;
 463
 464         enable_ipu_clock();
 465         imx_setup_hdmi();
 466         /* Turn on LDB0,IPU,IPU DI0 clocks */
 467         reg = __raw_readl(&mxc_ccm->CCGR3);
 468         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 469         writel(reg, &mxc_ccm->CCGR3);
 470
 471         /* set LDB0, LDB1 clk select to 011/011 */
 472         reg = readl(&mxc_ccm->cs2cdr);
 473         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 474                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 475         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 476               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 477         writel(reg, &mxc_ccm->cs2cdr);
 478
 479         reg = readl(&mxc_ccm->cscmr2);
 480         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 481         writel(reg, &mxc_ccm->cscmr2);
 482
 483         reg = readl(&mxc_ccm->chsccdr);
 484         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 485                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 486         writel(reg, &mxc_ccm->chsccdr);
 487
 488         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 489              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 490              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 491              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 492              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 493              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 494              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 495              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 496              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 497         writel(reg, &iomux->gpr[2]);
 498
 499         reg = readl(&iomux->gpr[3]);
 500         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 501             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 502                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 503         writel(reg, &iomux->gpr[3]);
 504
 505         /* LVDS Backlight GPIO on LVDS connector - output low */
 506         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 507         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 508 }
 509 #endif /* CONFIG_VIDEO_IPUV3 */
 510
 511 /* setup board specific PMIC */
 512 int power_init_board(void)
 513 {
 514         setup_pmic();
 515         return 0;
 516 }
 517
 518 #if defined(CONFIG_CMD_PCI)
 519 int imx6_pcie_toggle_reset(void)
 520 {
 521         if (board_type < GW_UNKNOWN) {
 522                 uint pin = gpio_cfg[board_type].pcie_rst;
 523                 gpio_request(pin, "pci_rst#");
 524                 gpio_direction_output(pin, 0);
 525                 mdelay(50);
 526                 gpio_direction_output(pin, 1);
 527         }
 528         return 0;
 529 }
 530
 531 /*
 532  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 533  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 534  * properly and assert reset for 100ms.
 535  */
 536 #define MAX_PCI_DEVS    32
 537 struct pci_dev {
 538         pci_dev_t devfn;
 539         unsigned short vendor;
 540         unsigned short device;
 541         unsigned short class;
 542         unsigned short busno; /* subbordinate busno */
 543         struct pci_dev *ppar;
 544 };
 545 struct pci_dev pci_devs[MAX_PCI_DEVS];
 546 int pci_devno;
 547 int pci_bridgeno;
 548
 549 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 550                          unsigned short vendor, unsigned short device,
 551                          unsigned short class)
 552 {
 553         int i;
 554         u32 dw;
 555         struct pci_dev *pdev = &pci_devs[pci_devno++];
 556
 557         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 558               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 559
 560         /* store array of devs for later use in device-tree fixup */
 561         pdev->devfn = dev;
 562         pdev->vendor = vendor;
 563         pdev->device = device;
 564         pdev->class = class;
 565         pdev->ppar = NULL;
 566         if (class == PCI_CLASS_BRIDGE_PCI)
 567                 pdev->busno = ++pci_bridgeno;
 568         else
 569                 pdev->busno = 0;
 570
 571         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 572         if (PCI_BUS(dev) == 0)
 573                 pdev->devfn = 0;
 574
 575         /* find dev's parent */
 576         for (i = 0; i < pci_devno; i++) {
 577                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 578                         pdev->ppar = &pci_devs[i];
 579                         break;
 580                 }
 581         }
 582
 583         /* assert downstream PERST# */
 584         if (vendor == PCI_VENDOR_ID_PLX &&
 585             (device & 0xfff0) == 0x8600 &&
 586             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 587                 debug("configuring PLX 860X downstream PERST#\n");
 588                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 589                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 590                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 591
 592                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 593                 dw |= 0xfe;   /* GPIO1-7 output high */
 594                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 595
 596                 mdelay(100);
 597         }
 598 }
 599 #endif /* CONFIG_CMD_PCI */
 600
 601 #ifdef CONFIG_SERIAL_TAG
 602 /*
 603  * called when setting up ATAGS before booting kernel
 604  * populate serialnum from the following (in order of priority):
 605  *   serial# env var
 606  *   eeprom
 607  */
 608 void get_board_serial(struct tag_serialnr *serialnr)
 609 {
 610         char *serial = env_get("serial#");
 611
 612         if (serial) {
 613                 serialnr->high = 0;
 614                 serialnr->low = simple_strtoul(serial, NULL, 10);
 615         } else if (ventana_info.model[0]) {
 616                 serialnr->high = 0;
 617                 serialnr->low = ventana_info.serial;
 618         } else {
 619                 serialnr->high = 0;
 620                 serialnr->low = 0;
 621         }
 622 }
 623 #endif
 624
 625 /*
 626  * Board Support
 627  */
 628
 629 int board_early_init_f(void)
 630 {
 631         setup_iomux_uart();
 632
 633 #if defined(CONFIG_VIDEO_IPUV3)
 634         setup_display();
 635 #endif
 636         return 0;
 637 }
 638
 639 int dram_init(void)
 640 {
 641         gd->ram_size = imx_ddr_size();
 642         return 0;
 643 }
 644
 645 int board_init(void)
 646 {
 647         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 648
 649         clrsetbits_le32(&iomuxc_regs->gpr[1],
 650                         IOMUXC_GPR1_OTG_ID_MASK,
 651                         IOMUXC_GPR1_OTG_ID_GPIO1);
 652
 653         /* address of linux boot parameters */
 654         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 655
 656         /* read Gateworks EEPROM into global struct (used later) */
 657         setup_ventana_i2c(0);
 658         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 659
 660 #ifdef CONFIG_CMD_NAND
 661         if (gpio_cfg[board_type].nand)
 662                 setup_gpmi_nand();
 663 #endif
 664 #ifdef CONFIG_MXC_SPI
 665         setup_spi();
 666 #endif
 667         setup_ventana_i2c(1);
 668         setup_ventana_i2c(2);
 669
 670 #ifdef CONFIG_SATA
 671         setup_sata();
 672 #endif
 673
 674         setup_iomux_gpio(board_type, &ventana_info);
 675
 676         return 0;
 677 }
 678
 679 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 680 /*
 681  * called during late init (after relocation and after board_init())
 682  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 683  * EEPROM read.
 684  */
 685 int checkboard(void)
 686 {
 687         struct ventana_board_info *info = &ventana_info;
 688         unsigned char buf[4];
 689         const char *p;
 690         int quiet; /* Quiet or minimal output mode */
 691
 692         quiet = 0;
 693         p = env_get("quiet");
 694         if (p)
 695                 quiet = simple_strtol(p, NULL, 10);
 696         else
 697                 env_set("quiet", "0");
 698
 699         puts("\nGateworks Corporation Copyright 2014\n");
 700         if (info->model[0]) {
 701                 printf("Model: %s\n", info->model);
 702                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 703                        info->mfgdate[0], info->mfgdate[1],
 704                        info->mfgdate[2], info->mfgdate[3]);
 705                 printf("Serial:%d\n", info->serial);
 706         } else {
 707                 puts("Invalid EEPROM - board will not function fully\n");
 708         }
 709         if (quiet)
 710                 return 0;
 711
 712         /* Display GSC firmware revision/CRC/status */
 713         gsc_info(0);
 714
 715         /* Display RTC */
 716         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 717                 printf("RTC:   %d\n",
 718                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 719         }
 720
 721         return 0;
 722 }
 723 #endif
 724
 725 #ifdef CONFIG_CMD_BMODE
 726 /*
 727  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 728  * see Table 8-11 and Table 5-9
 729  *  BOOT_CFG1[7] = 1 (boot from NAND)
 730  *  BOOT_CFG1[5] = 0 - raw NAND
 731  *  BOOT_CFG1[4] = 0 - default pad settings
 732  *  BOOT_CFG1[3:2] = 00 - devices = 1
 733  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 734  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 735  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 736  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 737  */
 738 static const struct boot_mode board_boot_modes[] = {
 739         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 740         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 741         { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
 742         { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
 743         { NULL, 0 },
 744 };
 745 #endif
 746
 747 /* late init */
 748 int misc_init_r(void)
 749 {
 750         struct ventana_board_info *info = &ventana_info;
 751         char buf[256];
 752         int i;
 753
 754         /* set env vars based on EEPROM data */
 755         if (ventana_info.model[0]) {
 756                 char str[16], fdt[36];
 757                 char *p;
 758                 const char *cputype = "";
 759
 760                 /*
 761                  * FDT name will be prefixed with CPU type.  Three versions
 762                  * will be created each increasingly generic and bootloader
 763                  * env scripts will try loading each from most specific to
 764                  * least.
 765                  */
 766                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 767                     is_cpu_type(MXC_CPU_MX6D))
 768                         cputype = "imx6q";
 769                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 770                          is_cpu_type(MXC_CPU_MX6SOLO))
 771                         cputype = "imx6dl";
 772                 env_set("soctype", cputype);
 773                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 774                         env_set("flash_layout", "large");
 775                 else
 776                         env_set("flash_layout", "normal");
 777                 memset(str, 0, sizeof(str));
 778                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 779                         str[i] = tolower(info->model[i]);
 780                 env_set("model", str);
 781                 if (!env_get("fdt_file")) {
 782                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 783                         env_set("fdt_file", fdt);
 784                 }
 785                 p = strchr(str, '-');
 786                 if (p) {
 787                         *p++ = 0;
 788
 789                         env_set("model_base", str);
 790                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 791                         env_set("fdt_file1", fdt);
 792                         if (board_type != GW551x &&
 793                             board_type != GW552x &&
 794                             board_type != GW553x &&
 795                             board_type != GW560x)
 796                                 str[4] = 'x';
 797                         str[5] = 'x';
 798                         str[6] = 0;
 799                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 800                         env_set("fdt_file2", fdt);
 801                 }
 802
 803                 /* initialize env from EEPROM */
 804                 if (test_bit(EECONFIG_ETH0, info->config) &&
 805                     !env_get("ethaddr")) {
 806                         eth_env_set_enetaddr("ethaddr", info->mac0);
 807                 }
 808                 if (test_bit(EECONFIG_ETH1, info->config) &&
 809                     !env_get("eth1addr")) {
 810                         eth_env_set_enetaddr("eth1addr", info->mac1);
 811                 }
 812
 813                 /* board serial-number */
 814                 sprintf(str, "%6d", info->serial);
 815                 env_set("serial#", str);
 816
 817                 /* memory MB */
 818                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 819                 env_set("mem_mb", str);
 820         }
 821
 822         /* Set a non-initialized hwconfig based on board configuration */
 823         if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
 824                 buf[0] = 0;
 825                 if (gpio_cfg[board_type].rs232_en)
 826                         strcat(buf, "rs232;");
 827                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 828                         char buf1[32];
 829                         sprintf(buf1, "dio%d:mode=gpio;", i);
 830                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 831                                 strcat(buf, buf1);
 832                 }
 833                 env_set("hwconfig", buf);
 834         }
 835
 836         /* setup baseboard specific GPIO based on board and env */
 837         setup_board_gpio(board_type, info);
 838
 839 #ifdef CONFIG_CMD_BMODE
 840         add_board_boot_modes(board_boot_modes);
 841 #endif
 842
 843         /* disable boot watchdog */
 844         gsc_boot_wd_disable();
 845
 846         return 0;
 847 }
 848
 849 #ifdef CONFIG_OF_BOARD_SETUP
 850
 851 static int ft_sethdmiinfmt(void *blob, char *mode)
 852 {
 853         int off;
 854
 855         if (!mode)
 856                 return -EINVAL;
 857
 858         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 859         if (off < 0)
 860                 return off;
 861
 862         if (0 == strcasecmp(mode, "yuv422bt656")) {
 863                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 864                              0x00, 0x00, 0x00 };
 865                 mode = "422_ccir";
 866                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 867                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 868                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 869                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 870                 printf("   set HDMI input mode to %s\n", mode);
 871         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 872                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 873                              0x82, 0x81, 0x00 };
 874                 mode = "422_smp";
 875                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 876                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 877                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 878                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 879                 printf("   set HDMI input mode to %s\n", mode);
 880         } else {
 881                 return -EINVAL;
 882         }
 883
 884         return 0;
 885 }
 886
 887 #if defined(CONFIG_CMD_PCI)
 888 #define PCI_ID(x) ( \
 889         (PCI_BUS(x->devfn)<<16)| \
 890         (PCI_DEV(x->devfn)<<11)| \
 891         (PCI_FUNC(x->devfn)<<8) \
 892         )
 893 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 894 {
 895         uint32_t reg[5];
 896         char node[32];
 897         int np;
 898
 899         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 900                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 901
 902         np = fdt_subnode_offset(blob, par, node);
 903         if (np >= 0)
 904                 return np;
 905         np = fdt_add_subnode(blob, par, node);
 906         if (np < 0) {
 907                 printf("   %s failed: no space\n", __func__);
 908                 return np;
 909         }
 910
 911         memset(reg, 0, sizeof(reg));
 912         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 913         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 914
 915         return np;
 916 }
 917
 918 /* build a path of nested PCI devs for all bridges passed through */
 919 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 920 {
 921         struct pci_dev *bridges[MAX_PCI_DEVS];
 922         int k, np;
 923
 924         /* build list of parents */
 925         np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
 926         if (np < 0)
 927                 return np;
 928
 929         k = 0;
 930         while (dev) {
 931                 bridges[k++] = dev;
 932                 dev = dev->ppar;
 933         };
 934
 935         /* now add them the to DT in reverse order */
 936         while (k--) {
 937                 np = fdt_add_pci_node(blob, np, bridges[k]);
 938                 if (np < 0)
 939                         break;
 940         }
 941
 942         return np;
 943 }
 944
 945 /*
 946  * The GW16082 has a hardware errata errata such that it's
 947  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 948  * of this normal PCI interrupt swizzling will not work so we will
 949  * provide an irq-map via device-tree.
 950  */
 951 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 952 {
 953         int len;
 954         int host;
 955         uint32_t imap_new[8*4*4];
 956         const uint32_t *imap;
 957         uint32_t irq[4];
 958         uint32_t reg[4];
 959         int i;
 960
 961         /* build irq-map based on host controllers map */
 962         host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
 963         if (host < 0) {
 964                 printf("   %s failed: missing host\n", __func__);
 965                 return host;
 966         }
 967
 968         /* use interrupt data from root complex's node */
 969         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 970         if (!imap || len != 128) {
 971                 printf("   %s failed: invalid interrupt-map\n",
 972                        __func__);
 973                 return -FDT_ERR_NOTFOUND;
 974         }
 975
 976         /* obtain irq's of host controller in pin order */
 977         for (i = 0; i < 4; i++)
 978                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 979
 980         /*
 981          * determine number of swizzles necessary:
 982          *   For each bridge we pass through we need to swizzle
 983          *   the number of the slot we are on.
 984          */
 985         struct pci_dev *d;
 986         int b;
 987         b = 0;
 988         d = dev->ppar;
 989         while(d && d->ppar) {
 990                 b += PCI_DEV(d->devfn);
 991                 d = d->ppar;
 992         }
 993
 994         /* create new irq mappings for slots12-15
 995          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
 996          * J3    AD28    12     INTD      INTA
 997          * J4    AD29    13     INTC      INTD
 998          * J5    AD30    14     INTB      INTC
 999          * J2    AD31    15     INTA      INTB
1000          */
1001         for (i = 0; i < 4; i++) {
1002                 /* addr matches bus:dev:func */
1003                 u32 addr = dev->busno << 16 | (12+i) << 11;
1004
1005                 /* default cells from root complex */
1006                 memcpy(&imap_new[i*32], imap, 128);
1007                 /* first cell is PCI device address (BDF) */
1008                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1009                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1010                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1011                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1012                 /* third cell is pin */
1013                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1014                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1015                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1016                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1017                 /* sixth cell is relative interrupt */
1018                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1019                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1020                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1021                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1022         }
1023         fdt_setprop(blob, np, "interrupt-map", imap_new,
1024                     sizeof(imap_new));
1025         reg[0] = cpu_to_fdt32(0xfff00);
1026         reg[1] = 0;
1027         reg[2] = 0;
1028         reg[3] = cpu_to_fdt32(0x7);
1029         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1030         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1031         fdt_setprop_string(blob, np, "device_type", "pci");
1032         fdt_setprop_cell(blob, np, "#address-cells", 3);
1033         fdt_setprop_cell(blob, np, "#size-cells", 2);
1034         printf("   Added custom interrupt-map for GW16082\n");
1035
1036         return 0;
1037 }
1038
1039 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1040 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1041 {
1042         char *tmp, *end;
1043         char mac[16];
1044         unsigned char mac_addr[6];
1045         int j;
1046
1047         sprintf(mac, "eth1addr");
1048         tmp = env_get(mac);
1049         if (tmp) {
1050                 for (j = 0; j < 6; j++) {
1051                         mac_addr[j] = tmp ?
1052                                       simple_strtoul(tmp, &end,16) : 0;
1053                         if (tmp)
1054                                 tmp = (*end) ? end+1 : end;
1055                 }
1056                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1057                             sizeof(mac_addr));
1058                 printf("   Added mac addr for eth1\n");
1059                 return 0;
1060         }
1061
1062         return -1;
1063 }
1064
1065 /*
1066  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1067  * we will walk the PCI bus and add bridge nodes up to the device receiving
1068  * the fixup.
1069  */
1070 void ft_board_pci_fixup(void *blob, bd_t *bd)
1071 {
1072         int i, np;
1073         struct pci_dev *dev;
1074
1075         for (i = 0; i < pci_devno; i++) {
1076                 dev = &pci_devs[i];
1077
1078                 /*
1079                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1080                  * an EEPROM at i2c1-0x50.
1081                  */
1082                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1083                     (dev->device == 0x8240) &&
1084                     (i2c_set_bus_num(1) == 0) &&
1085                     (i2c_probe(0x50) == 0))
1086                 {
1087                         np = fdt_add_pci_path(blob, dev);
1088                         if (np > 0)
1089                                 fdt_fixup_gw16082(blob, np, dev);
1090                 }
1091
1092                 /* ethernet1 mac address */
1093                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1094                          (dev->device == 0x4380))
1095                 {
1096                         np = fdt_add_pci_path(blob, dev);
1097                         if (np > 0)
1098                                 fdt_fixup_sky2(blob, np, dev);
1099                 }
1100         }
1101 }
1102 #endif /* if defined(CONFIG_CMD_PCI) */
1103
1104 void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1105 {
1106         int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1107
1108         if (off) {
1109                 fdt_delprop(blob, off, "ext-reset-output");
1110                 fdt_delprop(blob, off, "fsl,ext-reset-output");
1111         }
1112 }
1113
1114 /*
1115  * called prior to booting kernel or by 'fdt boardsetup' command
1116  *
1117  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1118  *  - mtd partitions based on mtdparts/mtdids env
1119  *  - system-serial (board serial num from EEPROM)
1120  *  - board (full model from EEPROM)
1121  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1122  */
1123 #define WDOG1_ADDR      0x20bc000
1124 #define WDOG2_ADDR      0x20c0000
1125 #define GPIO3_ADDR      0x20a4000
1126 #define USDHC3_ADDR     0x2198000
1127 #define PWM0_ADDR       0x2080000
1128 int ft_board_setup(void *blob, bd_t *bd)
1129 {
1130         struct ventana_board_info *info = &ventana_info;
1131         struct ventana_eeprom_config *cfg;
1132         static const struct node_info nodes[] = {
1133                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1134                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1135         };
1136         const char *model = env_get("model");
1137         const char *display = env_get("display");
1138         int i;
1139         char rev = 0;
1140
1141         /* determine board revision */
1142         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1143                 if (ventana_info.model[i] >= 'A') {
1144                         rev = ventana_info.model[i];
1145                         break;
1146                 }
1147         }
1148
1149         if (env_get("fdt_noauto")) {
1150                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1151                 return 0;
1152         }
1153
1154         if (test_bit(EECONFIG_NAND, info->config)) {
1155                 /* Update partition nodes using info from mtdparts env var */
1156                 puts("   Updating MTD partitions...\n");
1157                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1158         }
1159
1160         /* Update display timings from display env var */
1161         if (display) {
1162                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1163                                       display) >= 0)
1164                         printf("   Set display timings for %s...\n", display);
1165         }
1166
1167         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1168
1169         /* board serial number */
1170         fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1171                     strlen(env_get("serial#")) + 1);
1172
1173         /* board (model contains model from device-tree) */
1174         fdt_setprop(blob, 0, "board", info->model,
1175                     strlen((const char *)info->model) + 1);
1176
1177         /* set desired digital video capture format */
1178         ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1179
1180         /*
1181          * Board model specific fixups
1182          */
1183         switch (board_type) {
1184         case GW51xx:
1185                 /*
1186                  * disable wdog node for GW51xx-A/B to work around
1187                  * errata causing wdog timer to be unreliable.
1188                  */
1189                 if (rev >= 'A' && rev < 'C') {
1190                         i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1191                                                           WDOG1_ADDR);
1192                         if (i)
1193                                 fdt_status_disabled(blob, i);
1194                 }
1195
1196                 /* GW51xx-E adds WDOG1_B external reset */
1197                 if (rev < 'E')
1198                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1199                 break;
1200
1201         case GW52xx:
1202                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1203                 if (info->model[4] == '2') {
1204                         u32 handle = 0;
1205                         u32 *range = NULL;
1206
1207                         i = fdt_node_offset_by_compatible(blob, -1,
1208                                                           "fsl,imx6q-pcie");
1209                         if (i)
1210                                 range = (u32 *)fdt_getprop(blob, i,
1211                                                            "reset-gpio", NULL);
1212
1213                         if (range) {
1214                                 i = fdt_node_offset_by_compat_reg(blob,
1215                                         "fsl,imx6q-gpio", GPIO3_ADDR);
1216                                 if (i)
1217                                         handle = fdt_get_phandle(blob, i);
1218                                 if (handle) {
1219                                         range[0] = cpu_to_fdt32(handle);
1220                                         range[1] = cpu_to_fdt32(23);
1221                                 }
1222                         }
1223
1224                         /* these have broken usd_vsel */
1225                         if (strstr((const char *)info->model, "SP318-B") ||
1226                             strstr((const char *)info->model, "SP331-B"))
1227                                 gpio_cfg[board_type].usd_vsel = 0;
1228
1229                         /* GW522x-B adds WDOG1_B external reset */
1230                         if (rev < 'B')
1231                                 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1232                 }
1233
1234                 /* GW520x-E adds WDOG1_B external reset */
1235                 else if (info->model[4] == '0' && rev < 'E')
1236                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1237                 break;
1238
1239         case GW53xx:
1240                 /* GW53xx-E adds WDOG1_B external reset */
1241                 if (rev < 'E')
1242                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1243                 break;
1244
1245         case GW54xx:
1246                 /*
1247                  * disable serial2 node for GW54xx for compatibility with older
1248                  * 3.10.x kernel that improperly had this node enabled in the DT
1249                  */
1250                 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1251                                         0);
1252
1253                 /* GW54xx-E adds WDOG2_B external reset */
1254                 if (rev < 'E')
1255                         ft_board_wdog_fixup(blob, WDOG2_ADDR);
1256                 break;
1257
1258         case GW551x:
1259                 /*
1260                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1261                  * causing non functional digital video in (it is not hooked up)
1262                  */
1263                 if (rev == 'A') {
1264                         u32 *range = NULL;
1265                         int len;
1266                         const u32 *handle = NULL;
1267
1268                         i = fdt_node_offset_by_compatible(blob, -1,
1269                                                 "fsl,imx-tda1997x-video");
1270                         if (i)
1271                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1272                                                      NULL);
1273                         if (handle)
1274                                 i = fdt_node_offset_by_phandle(blob,
1275                                                         fdt32_to_cpu(*handle));
1276                         if (i)
1277                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1278                                                            &len);
1279                         if (range) {
1280                                 len /= sizeof(u32);
1281                                 for (i = 0; i < len; i += 6) {
1282                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1283                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1284                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1285                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1286                                             mux_reg == 0x260 &&
1287                                             conf_reg == 0x630)
1288                                                 range[i+3] = cpu_to_fdt32(0x5);
1289                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1290                                                  mux_reg == 0x08c &&
1291                                                  conf_reg == 0x3a0)
1292                                                 range[i+3] = cpu_to_fdt32(0x5);
1293                                 }
1294                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1295                                                     len);
1296                         }
1297
1298                         /* set BT656 video format */
1299                         ft_sethdmiinfmt(blob, "yuv422bt656");
1300                 }
1301
1302                 /* GW551x-C adds WDOG1_B external reset */
1303                 if (rev < 'C')
1304                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1305                 break;
1306         case GW5901:
1307         case GW5902:
1308                 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1309                 if (rev < 'B')
1310                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1311                 break;
1312         }
1313
1314         /* Configure DIO */
1315         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1316                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1317                 char arg[10];
1318
1319                 sprintf(arg, "dio%d", i);
1320                 if (!hwconfig(arg))
1321                         continue;
1322                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1323                 {
1324                         phys_addr_t addr;
1325                         int off;
1326
1327                         printf("   Enabling pwm%d for DIO%d\n",
1328                                cfg->pwm_param, i);
1329                         addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1330                         off = fdt_node_offset_by_compat_reg(blob,
1331                                                             "fsl,imx6q-pwm",
1332                                                             addr);
1333                         if (off)
1334                                 fdt_status_okay(blob, off);
1335                 }
1336         }
1337
1338         /* remove no-1-8-v if UHS-I support is present */
1339         if (gpio_cfg[board_type].usd_vsel) {
1340                 debug("Enabling UHS-I support\n");
1341                 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1342                                                   USDHC3_ADDR);
1343                 if (i)
1344                         fdt_delprop(blob, i, "no-1-8-v");
1345         }
1346
1347 #if defined(CONFIG_CMD_PCI)
1348         if (!env_get("nopcifixup"))
1349                 ft_board_pci_fixup(blob, bd);
1350 #endif
1351
1352         /*
1353          * Peripheral Config:
1354          *  remove nodes by alias path if EEPROM config tells us the
1355          *  peripheral is not loaded on the board.
1356          */
1357         if (env_get("fdt_noconfig")) {
1358                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1359                 return 0;
1360         }
1361         cfg = econfig;
1362         while (cfg->name) {
1363                 if (!test_bit(cfg->bit, info->config)) {
1364                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1365                                                cfg->dtalias : cfg->name);
1366                 }
1367                 cfg++;
1368         }
1369
1370         return 0;
1371 }
1372 #endif /* CONFIG_OF_BOARD_SETUP */
1373
1374 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1375         .reg = (struct mxc_uart *)UART2_BASE,
1376 };
1377
1378 U_BOOT_DEVICE(ventana_serial) = {
1379         .name   = "serial_mxc",
1380         .platdata = &ventana_mxc_serial_plat,
1381 };