1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
17 #include <linux/compiler.h>
19 #include <asm/processor.h>
20 #include <asm/cache.h>
21 #include <asm/immap_85xx.h>
22 #include <asm/fsl_law.h>
23 #include <asm/fsl_serdes.h>
24 #include <asm/fsl_liodn.h>
27 #include "../common/qixis.h"
28 #include "../common/vsc3316_3308.h"
30 #include "t4240qds_qixis.h"
32 DECLARE_GLOBAL_DATA_PTR;
34 static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
35 {8, 8}, {9, 9}, {14, 14}, {15, 15} };
37 static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
38 {10, 10}, {11, 11}, {12, 12}, {13, 13} };
40 static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
41 {10, 11}, {11, 10}, {12, 2}, {13, 3} };
43 static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
44 {8, 9}, {9, 8}, {14, 1}, {15, 0} };
50 struct cpu_type *cpu = gd->arch.cpu;
53 printf("Board: %sQDS, ", cpu->name);
54 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
55 QIXIS_READ(id), QIXIS_READ(arch));
57 sw = QIXIS_READ(brdcfg[0]);
58 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
61 printf("vBank: %d\n", sw);
67 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
69 printf("FPGA: v%d (%s), build %d",
70 (int)QIXIS_READ(scver), qixis_read_tag(buf),
71 (int)qixis_read_minor());
72 /* the timestamp string contains "\n" at the end */
73 printf(" on %s", qixis_read_time(buf));
76 * Display the actual SERDES reference clocks as configured by the
77 * dip switches on the board. Note that the SWx registers could
78 * technically be set to force the reference clocks to match the
79 * values that the SERDES expects (or vice versa). For now, however,
80 * we just display both values and hope the user notices when they
83 puts("SERDES Reference Clocks: ");
84 sw = QIXIS_READ(brdcfg[2]);
85 for (i = 0; i < MAX_SERDES; i++) {
86 static const char * const freq[] = {
87 "100", "125", "156.25", "161.1328125"};
88 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
90 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
97 int select_i2c_ch_pca9547(u8 ch, int bus_num)
104 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
107 printf("%s: Cannot find udev for a bus %d\n", __func__,
112 ret = dm_i2c_write(dev, 0, &ch, 1);
114 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
117 puts("PCA: failed to select proper channel\n");
125 * read_voltage from sensor on I2C bus
126 * We use average of 4 readings, waiting for 532us befor another reading
128 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
129 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
131 static inline int read_voltage(void)
133 int i, ret, voltage_read = 0;
140 for (i = 0; i < NUM_READINGS; i++) {
142 ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR,
145 printf("%s: Cannot find udev for a bus %d\n", __func__,
150 ret = dm_i2c_read(dev,
151 I2C_VOL_MONITOR_BUS_V_OFFSET,
152 (void *)&vol_mon, 2);
154 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
155 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
158 printf("VID: failed to read core voltage\n");
161 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
162 printf("VID: Core voltage sensor error\n");
165 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
167 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
168 udelay(WAIT_FOR_ADC);
170 /* calculate the average */
171 voltage_read /= NUM_READINGS;
177 * We need to calculate how long before the voltage starts to drop or increase
178 * It returns with the loop count. Each loop takes several readings (532us)
180 static inline int wait_for_voltage_change(int vdd_last)
182 int timeout, vdd_current;
184 vdd_current = read_voltage();
185 /* wait until voltage starts to drop */
186 for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
187 timeout < 100; timeout++) {
188 vdd_current = read_voltage();
190 if (timeout >= 100) {
191 printf("VID: Voltage adjustment timeout\n");
198 * argument 'wait' is the time we know the voltage difference can be measured
199 * this function keeps reading the voltage until it is stable
201 static inline int wait_for_voltage_stable(int wait)
203 int timeout, vdd_current, vdd_last;
205 vdd_last = read_voltage();
206 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
207 /* wait until voltage is stable */
208 vdd_current = read_voltage();
209 for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
210 timeout < 100; timeout++) {
211 vdd_last = vdd_current;
212 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
213 vdd_current = read_voltage();
215 if (timeout >= 100) {
216 printf("VID: Voltage adjustment timeout\n");
223 static inline int set_voltage(u8 vid)
227 vdd_last = read_voltage();
228 QIXIS_WRITE(brdcfg[6], vid);
229 wait = wait_for_voltage_change(vdd_last);
232 debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
233 wait = wait ? wait : 1;
235 vdd_last = wait_for_voltage_stable(wait);
238 debug("VID: Current voltage is %d mV\n", vdd_last);
244 static int adjust_vdd(ulong vdd_override)
246 int re_enable = disable_interrupts();
247 ccsr_gur_t __iomem *gur =
248 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
251 int vdd_target, vdd_current, vdd_last;
253 unsigned long vdd_string_override;
255 static const uint16_t vdd[32] = {
288 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0);
290 debug("VID: I2c failed to switch channel\n");
295 /* get the voltage ID from fuse status register */
296 fusesr = in_be32(&gur->dcfg_fusesr);
297 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
298 FSL_CORENET_DCFG_FUSESR_VID_MASK;
299 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
300 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
301 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
303 vdd_target = vdd[vid];
305 /* check override variable for overriding VDD */
306 vdd_string = env_get("t4240qds_vdd_mv");
307 if (vdd_override == 0 && vdd_string &&
308 !strict_strtoul(vdd_string, 10, &vdd_string_override))
309 vdd_override = vdd_string_override;
310 if (vdd_override >= 819 && vdd_override <= 1212) {
311 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
312 debug("VDD override is %lu\n", vdd_override);
313 } else if (vdd_override != 0) {
314 printf("Invalid value.\n");
317 if (vdd_target == 0) {
318 debug("VID: VID not used\n");
322 /* round up and divice by 10 to get a value in mV */
323 vdd_target = DIV_ROUND_UP(vdd_target, 10);
324 debug("VID: vid = %d mV\n", vdd_target);
328 * Check current board VID setting
329 * Voltage regulator support output to 6.250mv step
330 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
331 * the lowest is (vid=0x7f) 0.81875V
333 vid_current = QIXIS_READ(brdcfg[6]);
334 vdd_current = 121250 - (vid_current - 0x40) * 625;
335 debug("VID: Current vid setting is (0x%x) %d mV\n",
336 vid_current, vdd_current/100);
339 * Read voltage monitor to check real voltage.
340 * Voltage monitor LSB is 4mv.
342 vdd_last = read_voltage();
344 printf("VID: Could not read voltage sensor abort VID adjustment\n");
348 debug("VID: Core voltage is at %d mV\n", vdd_last);
350 * Adjust voltage to at or 8mV above target.
351 * Each step of adjustment is 6.25mV.
352 * Stepping down too fast may cause over current.
354 while (vdd_last > 0 && vid_current < 0x80 &&
355 vdd_last > (vdd_target + 8)) {
357 vdd_last = set_voltage(vid_current);
360 * Check if we need to step up
361 * This happens when board voltage switch was set too low
363 while (vdd_last > 0 && vid_current >= 0x40 &&
364 vdd_last < vdd_target + 2) {
366 vdd_last = set_voltage(vid_current);
369 printf("VID: Core voltage %d mV\n", vdd_last);
379 /* Configure Crossbar switches for Front-Side SerDes Ports */
380 int config_frontside_crossbar_vsc3316(void)
382 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
383 u32 srds_prtcl_s1, srds_prtcl_s2;
386 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0);
390 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
391 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
392 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
393 switch (srds_prtcl_s1) {
396 /* swap first lane and third lane on slot1 */
397 vsc3316_fsm1_tx[0][1] = 14;
398 vsc3316_fsm1_tx[6][1] = 0;
399 vsc3316_fsm1_rx[1][1] = 2;
400 vsc3316_fsm1_rx[6][1] = 13;
407 /* swap first lane and third lane on slot2 */
408 vsc3316_fsm1_tx[2][1] = 8;
409 vsc3316_fsm1_tx[4][1] = 6;
410 vsc3316_fsm1_rx[2][1] = 10;
411 vsc3316_fsm1_rx[5][1] = 5;
413 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
416 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
422 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
423 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
424 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
425 switch (srds_prtcl_s2) {
428 /* swap first lane and third lane on slot3 */
429 vsc3316_fsm2_tx[2][1] = 11;
430 vsc3316_fsm2_tx[5][1] = 4;
431 vsc3316_fsm2_rx[2][1] = 9;
432 vsc3316_fsm2_rx[4][1] = 7;
445 /* swap first lane and third lane on slot4 */
446 vsc3316_fsm2_tx[6][1] = 3;
447 vsc3316_fsm2_tx[1][1] = 12;
448 vsc3316_fsm2_rx[0][1] = 1;
449 vsc3316_fsm2_rx[6][1] = 15;
451 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
454 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
463 int config_backside_crossbar_mux(void)
465 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
466 u32 srds_prtcl_s3, srds_prtcl_s4;
469 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
470 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
471 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
472 switch (srds_prtcl_s3) {
474 /* SerDes3 is not enabled */
480 /* SD3(0:7) => SLOT5(0:7) */
481 brdcfg = QIXIS_READ(brdcfg[12]);
482 brdcfg &= ~BRDCFG12_SD3MX_MASK;
483 brdcfg |= BRDCFG12_SD3MX_SLOT5;
484 QIXIS_WRITE(brdcfg[12], brdcfg);
502 /* SD3(4:7) => SLOT6(0:3) */
503 brdcfg = QIXIS_READ(brdcfg[12]);
504 brdcfg &= ~BRDCFG12_SD3MX_MASK;
505 brdcfg |= BRDCFG12_SD3MX_SLOT6;
506 QIXIS_WRITE(brdcfg[12], brdcfg);
509 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
514 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
515 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
516 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
517 switch (srds_prtcl_s4) {
519 /* SerDes4 is not enabled */
523 /* 10b, SD4(0:7) => SLOT7(0:7) */
524 brdcfg = QIXIS_READ(brdcfg[12]);
525 brdcfg &= ~BRDCFG12_SD4MX_MASK;
526 brdcfg |= BRDCFG12_SD4MX_SLOT7;
527 QIXIS_WRITE(brdcfg[12], brdcfg);
535 /* x1b, SD4(4:7) => SLOT8(0:3) */
536 brdcfg = QIXIS_READ(brdcfg[12]);
537 brdcfg &= ~BRDCFG12_SD4MX_MASK;
538 brdcfg |= BRDCFG12_SD4MX_SLOT8;
539 QIXIS_WRITE(brdcfg[12], brdcfg);
550 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
551 brdcfg = QIXIS_READ(brdcfg[12]);
552 brdcfg &= ~BRDCFG12_SD4MX_MASK;
553 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
554 QIXIS_WRITE(brdcfg[12], brdcfg);
557 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
565 int board_early_init_r(void)
567 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
568 int flash_esel = find_tlb_idx((void *)flashbase, 1);
571 * Remap Boot flash + PROMJET region to caching-inhibited
572 * so that flash can be erased properly.
575 /* Flush d-cache and invalidate i-cache of any FLASH data */
579 if (flash_esel == -1) {
580 /* very unlikely unless something is messed up */
581 puts("Error: Could not find TLB for FLASH BASE\n");
582 flash_esel = 2; /* give our best effort to continue */
584 /* invalidate existing TLB entry for flash + promjet */
585 disable_tlb(flash_esel);
588 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
589 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
590 0, flash_esel, BOOKE_PAGESZ_256M, 1);
592 /* Disable remote I2C connection to qixis fpga */
593 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
596 * Adjust core voltage according to voltage ID
597 * This function changes I2C mux to channel 2.
600 printf("Warning: Adjusting core voltage failed.\n");
602 /* Configure board SERDES ports crossbar */
603 config_frontside_crossbar_vsc3316();
604 config_backside_crossbar_mux();
605 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
610 unsigned long get_board_sys_clk(void)
612 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
613 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
614 /* use accurate clock measurement */
615 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
616 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
621 debug("SYS Clock measurement is: %d\n", val);
624 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
628 switch (sysclk_conf & 0x0F) {
629 case QIXIS_SYSCLK_83:
631 case QIXIS_SYSCLK_100:
633 case QIXIS_SYSCLK_125:
635 case QIXIS_SYSCLK_133:
637 case QIXIS_SYSCLK_150:
639 case QIXIS_SYSCLK_160:
641 case QIXIS_SYSCLK_166:
647 unsigned long get_board_ddr_clk(void)
649 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
650 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
651 /* use accurate clock measurement */
652 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
653 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
658 debug("DDR Clock measurement is: %d\n", val);
661 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
665 switch ((ddrclk_conf & 0x30) >> 4) {
666 case QIXIS_DDRCLK_100:
668 case QIXIS_DDRCLK_125:
670 case QIXIS_DDRCLK_133:
676 int misc_init_r(void)
679 void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
680 serdes_corenet_t *srds_regs;
681 u32 actual[MAX_SERDES];
682 u32 pllcr0, expected;
685 sw = QIXIS_READ(brdcfg[2]);
686 for (i = 0; i < MAX_SERDES; i++) {
687 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
690 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
693 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
696 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
699 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
704 for (i = 0; i < MAX_SERDES; i++) {
705 srds_regs = srds_base + i * 0x1000;
706 pllcr0 = srds_regs->bank[0].pllcr0;
707 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
708 if (expected != actual[i]) {
709 printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
710 i + 1, serdes_clock_to_string(expected),
711 serdes_clock_to_string(actual[i]));
718 int ft_board_setup(void *blob, bd_t *bd)
723 ft_cpu_setup(blob, bd);
725 base = env_get_bootm_low();
726 size = env_get_bootm_size();
728 fdt_fixup_memory(blob, (u64)base, (u64)size);
731 pci_of_setup(blob, bd);
734 fdt_fixup_liodn(blob);
735 fsl_fdt_fixup_dr_usb(blob, bd);
737 #ifdef CONFIG_SYS_DPAA_FMAN
738 fdt_fixup_fman_ethernet(blob);
739 fdt_fixup_board_enet(blob);
746 * This function is called by bdinfo to print detail board information.
747 * As an exmaple for future board, we organize the messages into
748 * several sections. If applicable, the message is in the format of
750 * It should aligned with normal output of bdinfo command.
752 * Voltage: Core, DDR and another configurable voltages
753 * Clock : Critical clocks which are not printed already
754 * RCW : RCW source if not printed already
755 * Misc : Other important information not in above catagories
757 void board_detail(void)
760 u8 brdcfg[16], dutcfg[16], rst_ctl;
762 static const char * const clk[] = {"66.67", "100", "125", "133.33"};
764 for (i = 0; i < 16; i++) {
765 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
766 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
770 if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) {
771 vdd = read_voltage();
773 printf("Core voltage= %d mV\n", vdd);
774 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
777 printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
780 printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
781 clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
784 rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
785 puts("RCW source = ");
793 puts("16-bit NOR\n");
799 puts("SPI 16-bit addressing\n");
802 puts("SPI 24-bit addressing\n");
805 puts("I2C normal addressing\n");
808 puts("I2C extended addressing\n");
814 puts("8-bit NAND, 2KB\n");
817 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
818 puts("Hard-coded RCW\n");
819 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
820 puts("8-bit NAND, 4KB\n");
827 rst_ctl = QIXIS_READ(rst_ctl);
828 puts("HRESET_REQ = ");
829 switch (rst_ctl & 0x30) {
834 puts("Assert HRESET\n");
837 puts("Reset system\n");
846 * Reverse engineering switch settings.
847 * Some bits cannot be figured out. They will be displayed as
848 * underscore in binary format. mask[] has those bits.
849 * Some bits are calculated differently than the actual switches
850 * if booting with overriding by FPGA.
852 void qixis_dump_switch(void)
858 * Any bit with 1 means that bit cannot be reverse engineered.
859 * It will be displayed as _ in binary format.
861 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
863 u8 brdcfg[16], dutcfg[16];
865 for (i = 0; i < 16; i++) {
866 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
867 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
871 sw[1] = (dutcfg[1] << 0x07) |
872 ((dutcfg[12] & 0xC0) >> 1) |
873 ((dutcfg[11] & 0xE0) >> 3) |
874 ((dutcfg[6] & 0x80) >> 6) |
875 ((dutcfg[1] & 0x80) >> 7);
876 sw[2] = ((brdcfg[1] & 0x0f) << 4) |
877 ((brdcfg[1] & 0x30) >> 2) |
878 ((brdcfg[1] & 0x40) >> 5) |
879 ((brdcfg[1] & 0x80) >> 7);
881 sw[4] = ((dutcfg[2] & 0x01) << 7) |
882 ((dutcfg[2] & 0x06) << 4) |
883 ((~QIXIS_READ(present)) & 0x10) |
884 ((brdcfg[3] & 0x80) >> 4) |
885 ((brdcfg[3] & 0x01) << 2) |
886 ((brdcfg[6] == 0x62) ? 3 :
887 ((brdcfg[6] == 0x5a) ? 2 :
888 ((brdcfg[6] == 0x5e) ? 1 : 0)));
889 sw[5] = ((brdcfg[0] & 0x0f) << 4) |
890 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
891 ((brdcfg[0] & 0x40) >> 5);
892 sw[6] = (brdcfg[11] & 0x20) |
893 ((brdcfg[5] & 0x02) << 3);
894 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
895 ((brdcfg[5] & 0x10) << 2);
896 sw[8] = ((brdcfg[12] & 0x08) << 4) |
897 ((brdcfg[12] & 0x03) << 5);
899 puts("DIP switch (reverse-engineering)\n");
900 for (i = 0; i < 9; i++) {
901 printf("SW%d = 0b%s (0x%02x)\n",
902 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
906 static int do_vdd_adjust(struct cmd_tbl *cmdtp,
913 return CMD_RET_USAGE;
914 if (!strict_strtoul(argv[1], 10, &override))
915 adjust_vdd(override); /* the value is checked by callee */
917 return CMD_RET_USAGE;
923 vdd_override, 2, 0, do_vdd_adjust,
925 "- override with the voltage specified in mV, eg. 1050"