board/freescale/t104xrdb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/mmu.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/mpc85xx_gpio.h>
  16 #include "ddr.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 void fsl_ddr_board_options(memctl_options_t *popts,
  21                                 dimm_params_t *pdimm,
  22                                 unsigned int ctrl_num)
  23 {
  24         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  25         ulong ddr_freq;
  26
  27         if (ctrl_num > 1) {
  28                 printf("Not supported controller number %d\n", ctrl_num);
  29                 return;
  30         }
  31         if (!pdimm->n_ranks)
  32                 return;
  33
  34         pbsp = udimms[0];
  35
  36         /* Get clk_adjust according to the board ddr
  37          * freqency and n_banks specified in board_specific_parameters table.
  38          */
  39         ddr_freq = get_ddr_freq(0) / 1000000;
  40         while (pbsp->datarate_mhz_high) {
  41                 if (pbsp->n_ranks == pdimm->n_ranks &&
  42                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  43                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  44                                 popts->clk_adjust = pbsp->clk_adjust;
  45                                 popts->wrlvl_start = pbsp->wrlvl_start;
  46                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  47                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  48                                 goto found;
  49                         }
  50                         pbsp_highest = pbsp;
  51                 }
  52                 pbsp++;
  53         }
  54
  55         if (pbsp_highest) {
  56                 printf("Error: board specific timing not found\n");
  57                 printf("for data rate %lu MT/s\n", ddr_freq);
  58                 printf("Trying to use the highest speed (%u) parameters\n",
  59                        pbsp_highest->datarate_mhz_high);
  60                 popts->clk_adjust = pbsp_highest->clk_adjust;
  61                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  62                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  63                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  64         } else {
  65                 panic("DIMM is not supported by this board");
  66         }
  67 found:
  68         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  69                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  70                 "wrlvl_ctrl_3 0x%x\n",
  71                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  72                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  73                 pbsp->wrlvl_ctl_3);
  74
  75         /*
  76          * Factors to consider for half-strength driver enable:
  77          *      - number of DIMMs installed
  78          */
  79 #ifdef CONFIG_SYS_FSL_DDR4
  80         popts->half_strength_driver_enable = 1;
  81         /* optimize cpo for erratum A-009942 */
  82         popts->cpo_sample = 0x59;
  83 #else
  84         popts->half_strength_driver_enable = 0;
  85 #endif
  86         /*
  87          * Write leveling override
  88          */
  89         popts->wrlvl_override = 1;
  90         popts->wrlvl_sample = 0xf;
  91
  92         /*
  93          * rtt and rtt_wr override
  94          */
  95         popts->rtt_override = 0;
  96
  97         /* Enable ZQ calibration */
  98         popts->zq_en = 1;
  99
 100         /* DHC_EN =1, ODT = 75 Ohm */
 101 #ifdef CONFIG_SYS_FSL_DDR4
 102         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
 103         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
 104                 DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
 105 #else
 106         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 107         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 108 #endif
 109 }
 110
 111 #if defined(CONFIG_DEEP_SLEEP)
 112 void board_mem_sleep_setup(void)
 113 {
 114         void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
 115
 116         /* does not provide HW signals for power management */
 117         clrbits_8(cpld_base + 0x17, 0x40);
 118         /* Disable MCKE isolation */
 119         gpio_set_value(2, 0);
 120         udelay(1);
 121 }
 122 #endif
 123
 124 int dram_init(void)
 125 {
 126         phys_size_t dram_size;
 127
 128 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 129         puts("Initializing....using SPD\n");
 130         dram_size = fsl_ddr_sdram();
 131 #else
 132         dram_size =  fsl_ddr_sdram_size();
 133 #endif
 134         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 135         dram_size *= 0x100000;
 136
 137 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 138         fsl_dp_resume();
 139 #endif
 140
 141         gd->ram_size = dram_size;
 142
 143         return 0;
 144 }