board/freescale/t1040qds/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/mmu.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/mpc85xx_gpio.h>
  16 #include <linux/delay.h>
  17 #include "ddr.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 void fsl_ddr_board_options(memctl_options_t *popts,
  22                                 dimm_params_t *pdimm,
  23                                 unsigned int ctrl_num)
  24 {
  25         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  26         ulong ddr_freq;
  27
  28         if (ctrl_num > 2) {
  29                 printf("Not supported controller number %d\n", ctrl_num);
  30                 return;
  31         }
  32         if (!pdimm->n_ranks)
  33                 return;
  34
  35         pbsp = udimms[0];
  36
  37         /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
  38          * freqency and n_banks specified in board_specific_parameters table.
  39          */
  40         ddr_freq = get_ddr_freq(0) / 1000000;
  41         while (pbsp->datarate_mhz_high) {
  42                 if (pbsp->n_ranks == pdimm->n_ranks &&
  43                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  44                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  45                                 popts->clk_adjust = pbsp->clk_adjust;
  46                                 popts->wrlvl_start = pbsp->wrlvl_start;
  47                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  48                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  49                                 goto found;
  50                         }
  51                         pbsp_highest = pbsp;
  52                 }
  53                 pbsp++;
  54         }
  55
  56         if (pbsp_highest) {
  57                 printf("Error: board specific timing not found\n");
  58                 printf("for data rate %lu MT/s\n", ddr_freq);
  59                 printf("Trying to use the highest speed (%u) parameters\n",
  60                        pbsp_highest->datarate_mhz_high);
  61                 popts->clk_adjust = pbsp_highest->clk_adjust;
  62                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  63                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  64                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  65         } else {
  66                 panic("DIMM is not supported by this board");
  67         }
  68 found:
  69         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  70                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  71                 "wrlvl_ctrl_3 0x%x\n",
  72                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  73                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  74                 pbsp->wrlvl_ctl_3);
  75
  76         /*
  77          * Factors to consider for half-strength driver enable:
  78          *      - number of DIMMs installed
  79          */
  80         popts->half_strength_driver_enable = 1;
  81         /*
  82          * Write leveling override
  83          */
  84         popts->wrlvl_override = 1;
  85         popts->wrlvl_sample = 0xf;
  86
  87         /*
  88          * rtt and rtt_wr override
  89          */
  90         popts->rtt_override = 0;
  91
  92         /* Enable ZQ calibration */
  93         popts->zq_en = 1;
  94
  95         /* DHC_EN =1, ODT = 75 Ohm */
  96 #ifdef CONFIG_SYS_FSL_DDR4
  97         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  98         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  99                           DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
 100
 101         /* optimize cpo for erratum A-009942 */
 102         popts->cpo_sample = 0x69;
 103 #else
 104         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 105         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 106 #endif
 107 }
 108
 109 #if defined(CONFIG_DEEP_SLEEP)
 110 void board_mem_sleep_setup(void)
 111 {
 112         void __iomem *qixis_base = (void *)QIXIS_BASE;
 113
 114         /* does not provide HW signals for power management */
 115         clrbits_8(qixis_base + 0x21, 0x2);
 116         /* Disable MCKE isolation */
 117         gpio_set_value(2, 0);
 118         udelay(1);
 119 }
 120 #endif
 121
 122 int dram_init(void)
 123 {
 124         phys_size_t dram_size;
 125
 126         puts("Initializing....using SPD\n");
 127
 128         dram_size = fsl_ddr_sdram();
 129
 130         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 131         dram_size *= 0x100000;
 132
 133         puts("    DDR: ");
 134
 135 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 136         fsl_dp_resume();
 137 #endif
 138
 139         gd->ram_size = dram_size;
 140
 141         return 0;
 142 }