board/freescale/t102xrdb/t102xrdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <i2c.h>
  10 #include <init.h>
  11 #include <netdev.h>
  12 #include <linux/compiler.h>
  13 #include <asm/mmu.h>
  14 #include <asm/processor.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_law.h>
  17 #include <asm/fsl_serdes.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <fm_eth.h>
  20 #include "t102xrdb.h"
  21 #ifdef CONFIG_TARGET_T1024RDB
  22 #include "cpld.h"
  23 #elif defined(CONFIG_TARGET_T1023RDB)
  24 #include <i2c.h>
  25 #include <mmc.h>
  26 #endif
  27 #include "../common/sleep.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #ifdef CONFIG_TARGET_T1023RDB
  32 enum {
  33         GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
  34         GPIO1_EMMC_SEL,
  35         GPIO3_GET_VERSION,             /* GPIO3_4/5, 00:RevB, 01: RevC */
  36         GPIO3_BRD_VER_MASK = 0x0c000000,
  37         GPIO3_OFFSET = 0x2000,
  38         I2C_GET_BANK,
  39         I2C_SET_BANK0,
  40         I2C_SET_BANK4,
  41 };
  42 #endif
  43
  44 int checkboard(void)
  45 {
  46         struct cpu_type *cpu = gd->arch.cpu;
  47         static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  48         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  49         u32 srds_s1;
  50
  51         srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  52         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  53
  54         printf("Board: %sRDB, ", cpu->name);
  55 #if defined(CONFIG_TARGET_T1024RDB)
  56         printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  57                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  58 #elif defined(CONFIG_TARGET_T1023RDB)
  59         printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
  60 #endif
  61         printf("boot from ");
  62
  63 #ifdef CONFIG_SDCARD
  64         puts("SD/MMC\n");
  65 #elif CONFIG_SPIFLASH
  66         puts("SPI\n");
  67 #elif defined(CONFIG_TARGET_T1024RDB)
  68         u8 reg;
  69
  70         reg = CPLD_READ(flash_csr);
  71
  72         if (reg & CPLD_BOOT_SEL) {
  73                 puts("NAND\n");
  74         } else {
  75                 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  76                 printf("NOR vBank%d\n", reg);
  77         }
  78 #elif defined(CONFIG_TARGET_T1023RDB)
  79 #ifdef CONFIG_NAND
  80         puts("NAND\n");
  81 #else
  82         printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
  83 #endif
  84 #endif
  85
  86         puts("SERDES Reference Clocks:\n");
  87         if (srds_s1 == 0x95)
  88                 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  89         else
  90                 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
  91
  92         return 0;
  93 }
  94
  95 #ifdef CONFIG_TARGET_T1024RDB
  96 static void board_mux_lane(void)
  97 {
  98         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  99         u32 srds_prtcl_s1;
 100         u8 reg = CPLD_READ(misc_ctl_status);
 101
 102         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 103                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 104         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 105
 106         if (srds_prtcl_s1 == 0x95) {
 107                 /* Route Lane B to PCIE */
 108                 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
 109         } else {
 110                 /* Route Lane B to SGMII */
 111                 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
 112         }
 113         CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
 114 }
 115 #endif
 116
 117 int board_early_init_f(void)
 118 {
 119 #if defined(CONFIG_DEEP_SLEEP)
 120         if (is_warm_boot())
 121                 fsl_dp_disable_console();
 122 #endif
 123
 124         return 0;
 125 }
 126
 127 int board_early_init_r(void)
 128 {
 129 #ifdef CONFIG_SYS_FLASH_BASE
 130         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 131         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 132         /*
 133          * Remap Boot flash region to caching-inhibited
 134          * so that flash can be erased properly.
 135          */
 136
 137         /* Flush d-cache and invalidate i-cache of any FLASH data */
 138         flush_dcache();
 139         invalidate_icache();
 140         if (flash_esel == -1) {
 141                 /* very unlikely unless something is messed up */
 142                 puts("Error: Could not find TLB for FLASH BASE\n");
 143                 flash_esel = 2; /* give our best effort to continue */
 144         } else {
 145                 /* invalidate existing TLB entry for flash + promjet */
 146                 disable_tlb(flash_esel);
 147         }
 148
 149         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 150                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 151                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 152 #endif
 153
 154 #ifdef CONFIG_TARGET_T1024RDB
 155         board_mux_lane();
 156 #endif
 157
 158         return 0;
 159 }
 160
 161 unsigned long get_board_sys_clk(void)
 162 {
 163         return CONFIG_SYS_CLK_FREQ;
 164 }
 165
 166 unsigned long get_board_ddr_clk(void)
 167 {
 168         return CONFIG_DDR_CLK_FREQ;
 169 }
 170
 171 #ifdef CONFIG_TARGET_T1024RDB
 172 void board_reset(void)
 173 {
 174         CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
 175 }
 176 #endif
 177
 178 int misc_init_r(void)
 179 {
 180         return 0;
 181 }
 182
 183 int ft_board_setup(void *blob, bd_t *bd)
 184 {
 185         phys_addr_t base;
 186         phys_size_t size;
 187
 188         ft_cpu_setup(blob, bd);
 189
 190         base = env_get_bootm_low();
 191         size = env_get_bootm_size();
 192
 193         fdt_fixup_memory(blob, (u64)base, (u64)size);
 194
 195 #ifdef CONFIG_PCI
 196         pci_of_setup(blob, bd);
 197 #endif
 198
 199         fdt_fixup_liodn(blob);
 200         fsl_fdt_fixup_dr_usb(blob, bd);
 201
 202 #ifdef CONFIG_SYS_DPAA_FMAN
 203         fdt_fixup_fman_ethernet(blob);
 204         fdt_fixup_board_enet(blob);
 205 #endif
 206
 207 #ifdef CONFIG_TARGET_T1023RDB
 208         if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
 209                 fdt_enable_nor(blob);
 210 #endif
 211
 212         return 0;
 213 }
 214
 215 #ifdef CONFIG_TARGET_T1023RDB
 216 /* Enable NOR flash for RevC */
 217 static void fdt_enable_nor(void *blob)
 218 {
 219         int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
 220
 221         if (nodeoff >= 0)
 222                 fdt_status_okay(blob, nodeoff);
 223         else
 224                 printf("WARNING unable to set status for NOR\n");
 225 }
 226
 227 int board_mmc_getcd(struct mmc *mmc)
 228 {
 229         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 230         u32 val = in_be32(&pgpio->gpdat);
 231
 232         /* GPIO1_14, 0: eMMC, 1: SD/MMC */
 233         val &= GPIO1_SD_SEL;
 234
 235         return val ? -1 : 1;
 236 }
 237
 238 int board_mmc_getwp(struct mmc *mmc)
 239 {
 240         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 241         u32 val = in_be32(&pgpio->gpdat);
 242
 243         val &= GPIO1_SD_SEL;
 244
 245         return val ? -1 : 0;
 246 }
 247
 248 static u32 t1023rdb_ctrl(u32 ctrl_type)
 249 {
 250         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 251         ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 252         u32 val, orig_bus = i2c_get_bus_num();
 253         u8 tmp;
 254
 255         switch (ctrl_type) {
 256         case GPIO1_SD_SEL:
 257                 val = in_be32(&pgpio->gpdat);
 258                 val |= GPIO1_SD_SEL;
 259                 out_be32(&pgpio->gpdat, val);
 260                 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 261                 break;
 262         case GPIO1_EMMC_SEL:
 263                 val = in_be32(&pgpio->gpdat);
 264                 val &= ~GPIO1_SD_SEL;
 265                 out_be32(&pgpio->gpdat, val);
 266                 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 267                 break;
 268         case GPIO3_GET_VERSION:
 269                 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
 270                          + GPIO3_OFFSET);
 271                 val = in_be32(&pgpio->gpdat);
 272                 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
 273                 if (val == 0x3) /* GPIO3_4/5 not used on RevB */
 274                         val = 0;
 275                 return val;
 276         case I2C_GET_BANK:
 277                 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
 278                 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
 279                 tmp &= 0x7;
 280                 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
 281                 i2c_set_bus_num(orig_bus);
 282                 return tmp;
 283         case I2C_SET_BANK0:
 284                 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
 285                 tmp = 0x0;
 286                 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
 287                 tmp = 0xf8;
 288                 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
 289                 /* asserting HRESET_REQ */
 290                 out_be32(&gur->rstcr, 0x2);
 291                 break;
 292         case I2C_SET_BANK4:
 293                 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
 294                 tmp = 0x1;
 295                 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
 296                 tmp = 0xf8;
 297                 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
 298                 out_be32(&gur->rstcr, 0x2);
 299                 break;
 300         default:
 301                 break;
 302         }
 303         return 0;
 304 }
 305
 306 static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 307                     char * const argv[])
 308 {
 309         if (argc < 2)
 310                 return CMD_RET_USAGE;
 311         if (!strcmp(argv[1], "bank0"))
 312                 t1023rdb_ctrl(I2C_SET_BANK0);
 313         else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
 314                 t1023rdb_ctrl(I2C_SET_BANK4);
 315         else if (!strcmp(argv[1], "sd"))
 316                 t1023rdb_ctrl(GPIO1_SD_SEL);
 317         else if (!strcmp(argv[1], "emmc"))
 318                 t1023rdb_ctrl(GPIO1_EMMC_SEL);
 319         else
 320                 return CMD_RET_USAGE;
 321         return 0;
 322 }
 323
 324 U_BOOT_CMD(
 325         switch, 2, 0, switch_cmd,
 326         "for bank0/bank4/sd/emmc switch control in runtime",
 327         "command (e.g. switch bank4)"
 328 );
 329 #endif