board/freescale/t102xrdb/t102xrdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <env.h>
  10 #include <fdt_support.h>
  11 #include <i2c.h>
  12 #include <image.h>
  13 #include <init.h>
  14 #include <netdev.h>
  15 #include <linux/compiler.h>
  16 #include <asm/mmu.h>
  17 #include <asm/processor.h>
  18 #include <asm/immap_85xx.h>
  19 #include <asm/fsl_law.h>
  20 #include <asm/fsl_serdes.h>
  21 #include <asm/fsl_liodn.h>
  22 #include <fm_eth.h>
  23 #include "t102xrdb.h"
  24 #ifdef CONFIG_TARGET_T1024RDB
  25 #include "cpld.h"
  26 #elif defined(CONFIG_TARGET_T1023RDB)
  27 #include <i2c.h>
  28 #include <mmc.h>
  29 #endif
  30 #include "../common/sleep.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifdef CONFIG_TARGET_T1023RDB
  35 enum {
  36         GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
  37         GPIO1_EMMC_SEL,
  38         GPIO3_GET_VERSION,             /* GPIO3_4/5, 00:RevB, 01: RevC */
  39         GPIO3_BRD_VER_MASK = 0x0c000000,
  40         GPIO3_OFFSET = 0x2000,
  41         I2C_GET_BANK,
  42         I2C_SET_BANK0,
  43         I2C_SET_BANK4,
  44 };
  45 #endif
  46
  47 int checkboard(void)
  48 {
  49         struct cpu_type *cpu = gd->arch.cpu;
  50         static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  51         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  52         u32 srds_s1;
  53
  54         srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  55         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  56
  57         printf("Board: %sRDB, ", cpu->name);
  58 #if defined(CONFIG_TARGET_T1024RDB)
  59         printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  60                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  61 #elif defined(CONFIG_TARGET_T1023RDB)
  62         printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
  63 #endif
  64         printf("boot from ");
  65
  66 #ifdef CONFIG_SDCARD
  67         puts("SD/MMC\n");
  68 #elif CONFIG_SPIFLASH
  69         puts("SPI\n");
  70 #elif defined(CONFIG_TARGET_T1024RDB)
  71         u8 reg;
  72
  73         reg = CPLD_READ(flash_csr);
  74
  75         if (reg & CPLD_BOOT_SEL) {
  76                 puts("NAND\n");
  77         } else {
  78                 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  79                 printf("NOR vBank%d\n", reg);
  80         }
  81 #elif defined(CONFIG_TARGET_T1023RDB)
  82 #ifdef CONFIG_MTD_RAW_NAND
  83         puts("NAND\n");
  84 #else
  85         printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
  86 #endif
  87 #endif
  88
  89         puts("SERDES Reference Clocks:\n");
  90         if (srds_s1 == 0x95)
  91                 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  92         else
  93                 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
  94
  95         return 0;
  96 }
  97
  98 #ifdef CONFIG_TARGET_T1024RDB
  99 static void board_mux_lane(void)
 100 {
 101         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 102         u32 srds_prtcl_s1;
 103         u8 reg = CPLD_READ(misc_ctl_status);
 104
 105         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 106                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 107         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 108
 109         if (srds_prtcl_s1 == 0x95) {
 110                 /* Route Lane B to PCIE */
 111                 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
 112         } else {
 113                 /* Route Lane B to SGMII */
 114                 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
 115         }
 116         CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
 117 }
 118 #endif
 119
 120 int board_early_init_f(void)
 121 {
 122 #if defined(CONFIG_DEEP_SLEEP)
 123         if (is_warm_boot())
 124                 fsl_dp_disable_console();
 125 #endif
 126
 127         return 0;
 128 }
 129
 130 int board_early_init_r(void)
 131 {
 132 #ifdef CONFIG_SYS_FLASH_BASE
 133         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 134         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 135         /*
 136          * Remap Boot flash region to caching-inhibited
 137          * so that flash can be erased properly.
 138          */
 139
 140         /* Flush d-cache and invalidate i-cache of any FLASH data */
 141         flush_dcache();
 142         invalidate_icache();
 143         if (flash_esel == -1) {
 144                 /* very unlikely unless something is messed up */
 145                 puts("Error: Could not find TLB for FLASH BASE\n");
 146                 flash_esel = 2; /* give our best effort to continue */
 147         } else {
 148                 /* invalidate existing TLB entry for flash + promjet */
 149                 disable_tlb(flash_esel);
 150         }
 151
 152         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 153                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 154                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 155 #endif
 156
 157 #ifdef CONFIG_TARGET_T1024RDB
 158         board_mux_lane();
 159 #endif
 160
 161         return 0;
 162 }
 163
 164 unsigned long get_board_sys_clk(void)
 165 {
 166         return CONFIG_SYS_CLK_FREQ;
 167 }
 168
 169 unsigned long get_board_ddr_clk(void)
 170 {
 171         return CONFIG_DDR_CLK_FREQ;
 172 }
 173
 174 #ifdef CONFIG_TARGET_T1024RDB
 175 void board_reset(void)
 176 {
 177         CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
 178 }
 179 #endif
 180
 181 int misc_init_r(void)
 182 {
 183         return 0;
 184 }
 185
 186 int ft_board_setup(void *blob, bd_t *bd)
 187 {
 188         phys_addr_t base;
 189         phys_size_t size;
 190
 191         ft_cpu_setup(blob, bd);
 192
 193         base = env_get_bootm_low();
 194         size = env_get_bootm_size();
 195
 196         fdt_fixup_memory(blob, (u64)base, (u64)size);
 197
 198 #ifdef CONFIG_PCI
 199         pci_of_setup(blob, bd);
 200 #endif
 201
 202         fdt_fixup_liodn(blob);
 203         fsl_fdt_fixup_dr_usb(blob, bd);
 204
 205 #ifdef CONFIG_SYS_DPAA_FMAN
 206         fdt_fixup_fman_ethernet(blob);
 207         fdt_fixup_board_enet(blob);
 208 #endif
 209
 210 #ifdef CONFIG_TARGET_T1023RDB
 211         if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
 212                 fdt_enable_nor(blob);
 213 #endif
 214
 215         return 0;
 216 }
 217
 218 #ifdef CONFIG_TARGET_T1023RDB
 219 /* Enable NOR flash for RevC */
 220 static void fdt_enable_nor(void *blob)
 221 {
 222         int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
 223
 224         if (nodeoff >= 0)
 225                 fdt_status_okay(blob, nodeoff);
 226         else
 227                 printf("WARNING unable to set status for NOR\n");
 228 }
 229
 230 int board_mmc_getcd(struct mmc *mmc)
 231 {
 232         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 233         u32 val = in_be32(&pgpio->gpdat);
 234
 235         /* GPIO1_14, 0: eMMC, 1: SD/MMC */
 236         val &= GPIO1_SD_SEL;
 237
 238         return val ? -1 : 1;
 239 }
 240
 241 int board_mmc_getwp(struct mmc *mmc)
 242 {
 243         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 244         u32 val = in_be32(&pgpio->gpdat);
 245
 246         val &= GPIO1_SD_SEL;
 247
 248         return val ? -1 : 0;
 249 }
 250
 251 static u32 t1023rdb_ctrl(u32 ctrl_type)
 252 {
 253         ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 254         ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 255         u32 val;
 256         u8 tmp;
 257         int bus_num = I2C_PCA6408_BUS_NUM;
 258
 259 #ifdef CONFIG_DM_I2C
 260         struct udevice *dev;
 261         int ret;
 262
 263         ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
 264                                       1, &dev);
 265         if (ret) {
 266                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 267                        bus_num);
 268                 return ret;
 269         }
 270         switch (ctrl_type) {
 271         case GPIO1_SD_SEL:
 272                 val = in_be32(&pgpio->gpdat);
 273                 val |= GPIO1_SD_SEL;
 274                 out_be32(&pgpio->gpdat, val);
 275                 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 276                 break;
 277         case GPIO1_EMMC_SEL:
 278                 val = in_be32(&pgpio->gpdat);
 279                 val &= ~GPIO1_SD_SEL;
 280                 out_be32(&pgpio->gpdat, val);
 281                 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 282                 break;
 283         case GPIO3_GET_VERSION:
 284                 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
 285                          + GPIO3_OFFSET);
 286                 val = in_be32(&pgpio->gpdat);
 287                 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
 288                 if (val == 0x3) /* GPIO3_4/5 not used on RevB */
 289                         val = 0;
 290                 return val;
 291         case I2C_GET_BANK:
 292                 dm_i2c_read(dev, 0, &tmp, 1);
 293                 tmp &= 0x7;
 294                 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
 295                 return tmp;
 296         case I2C_SET_BANK0:
 297                 tmp = 0x0;
 298                 dm_i2c_write(dev, 1, &tmp, 1);
 299                 tmp = 0xf8;
 300                 dm_i2c_write(dev, 3, &tmp, 1);
 301                 /* asserting HRESET_REQ */
 302                 out_be32(&gur->rstcr, 0x2);
 303                 break;
 304         case I2C_SET_BANK4:
 305                 tmp = 0x1;
 306                 dm_i2c_write(dev, 1, &tmp, 1);
 307                 tmp = 0xf8;
 308                 dm_i2c_write(dev, 3, &tmp, 1);
 309                 out_be32(&gur->rstcr, 0x2);
 310                 break;
 311         default:
 312                 break;
 313         }
 314 #else
 315         u32 orig_bus;
 316
 317         orig_bus = i2c_get_bus_num();
 318
 319         switch (ctrl_type) {
 320         case GPIO1_SD_SEL:
 321                 val = in_be32(&pgpio->gpdat);
 322                 val |= GPIO1_SD_SEL;
 323                 out_be32(&pgpio->gpdat, val);
 324                 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 325                 break;
 326         case GPIO1_EMMC_SEL:
 327                 val = in_be32(&pgpio->gpdat);
 328                 val &= ~GPIO1_SD_SEL;
 329                 out_be32(&pgpio->gpdat, val);
 330                 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 331                 break;
 332         case GPIO3_GET_VERSION:
 333                 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
 334                          + GPIO3_OFFSET);
 335                 val = in_be32(&pgpio->gpdat);
 336                 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
 337                 if (val == 0x3) /* GPIO3_4/5 not used on RevB */
 338                         val = 0;
 339                 return val;
 340         case I2C_GET_BANK:
 341                 i2c_set_bus_num(bus_num);
 342                 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
 343                 tmp &= 0x7;
 344                 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
 345                 i2c_set_bus_num(orig_bus);
 346                 return tmp;
 347         case I2C_SET_BANK0:
 348                 i2c_set_bus_num(bus_num);
 349                 tmp = 0x0;
 350                 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
 351                 tmp = 0xf8;
 352                 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
 353                 /* asserting HRESET_REQ */
 354                 out_be32(&gur->rstcr, 0x2);
 355                 break;
 356         case I2C_SET_BANK4:
 357                 i2c_set_bus_num(bus_num);
 358                 tmp = 0x1;
 359                 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
 360                 tmp = 0xf8;
 361                 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
 362                 out_be32(&gur->rstcr, 0x2);
 363                 break;
 364         default:
 365                 break;
 366         }
 367 #endif
 368         return 0;
 369 }
 370
 371 static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 372                       char *const argv[])
 373 {
 374         if (argc < 2)
 375                 return CMD_RET_USAGE;
 376         if (!strcmp(argv[1], "bank0"))
 377                 t1023rdb_ctrl(I2C_SET_BANK0);
 378         else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
 379                 t1023rdb_ctrl(I2C_SET_BANK4);
 380         else if (!strcmp(argv[1], "sd"))
 381                 t1023rdb_ctrl(GPIO1_SD_SEL);
 382         else if (!strcmp(argv[1], "emmc"))
 383                 t1023rdb_ctrl(GPIO1_EMMC_SEL);
 384         else
 385                 return CMD_RET_USAGE;
 386         return 0;
 387 }
 388
 389 U_BOOT_CMD(
 390         switch, 2, 0, switch_cmd,
 391         "for bank0/bank4/sd/emmc switch control in runtime",
 392         "command (e.g. switch bank4)"
 393 );
 394 #endif