board/freescale/t102xrdb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/mmu.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/mpc85xx_gpio.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 struct board_specific_parameters {
  20         u32 n_ranks;
  21         u32 datarate_mhz_high;
  22         u32 rank_gb;
  23         u32 clk_adjust;
  24         u32 wrlvl_start;
  25         u32 wrlvl_ctl_2;
  26         u32 wrlvl_ctl_3;
  27 };
  28
  29 /*
  30  * datarate_mhz_high values need to be in ascending order
  31  */
  32 static const struct board_specific_parameters udimm0[] = {
  33         /*
  34          * memory controller 0
  35          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
  36          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
  37          */
  38         {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  39         {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  40         {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  41         {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  42         {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  43         {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  44         {}
  45 };
  46
  47 static const struct board_specific_parameters *udimms[] = {
  48         udimm0,
  49 };
  50
  51 void fsl_ddr_board_options(memctl_options_t *popts,
  52                            dimm_params_t *pdimm,
  53                            unsigned int ctrl_num)
  54 {
  55         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  56         ulong ddr_freq;
  57         struct cpu_type *cpu = gd->arch.cpu;
  58
  59         if (ctrl_num > 1) {
  60                 printf("Not supported controller number %d\n", ctrl_num);
  61                 return;
  62         }
  63         if (!pdimm->n_ranks)
  64                 return;
  65
  66         pbsp = udimms[0];
  67
  68         /* Get clk_adjust according to the board ddr freqency and n_banks
  69          * specified in board_specific_parameters table.
  70          */
  71         ddr_freq = get_ddr_freq(0) / 1000000;
  72         while (pbsp->datarate_mhz_high) {
  73                 if (pbsp->n_ranks == pdimm->n_ranks &&
  74                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  75                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  76                                 popts->clk_adjust = pbsp->clk_adjust;
  77                                 popts->wrlvl_start = pbsp->wrlvl_start;
  78                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  79                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  80                                 goto found;
  81                         }
  82                         pbsp_highest = pbsp;
  83                 }
  84                 pbsp++;
  85         }
  86
  87         if (pbsp_highest) {
  88                 printf("Error: board specific timing not found\n");
  89                 printf("for data rate %lu MT/s\n", ddr_freq);
  90                 printf("Trying to use the highest speed (%u) parameters\n",
  91                        pbsp_highest->datarate_mhz_high);
  92                 popts->clk_adjust = pbsp_highest->clk_adjust;
  93                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  94                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  95                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  96         } else {
  97                 panic("DIMM is not supported by this board");
  98         }
  99 found:
 100         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
 101               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
 102         debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
 103               pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
 104         debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
 105
 106         /*
 107          * Factors to consider for half-strength driver enable:
 108          *      - number of DIMMs installed
 109          */
 110         popts->half_strength_driver_enable = 0;
 111         /*
 112          * Write leveling override
 113          */
 114         popts->wrlvl_override = 1;
 115         popts->wrlvl_sample = 0xf;
 116
 117         /*
 118          * rtt and rtt_wr override
 119          */
 120         popts->rtt_override = 0;
 121
 122         /* Enable ZQ calibration */
 123         popts->zq_en = 1;
 124
 125         /* DHC_EN =1, ODT = 75 Ohm */
 126         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
 127         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
 128
 129         /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
 130          * force DDR bus width to 32bit for T1023
 131          */
 132         if (cpu->soc_ver == SVR_T1023)
 133                 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 134
 135 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 136         /* for DDR bus 32bit test on T1024 */
 137         popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 138 #endif
 139
 140 #ifdef CONFIG_TARGET_T1023RDB
 141         popts->wrlvl_ctl_2 = 0x07070606;
 142         popts->half_strength_driver_enable = 1;
 143         popts->cpo_sample = 0x43;
 144 #elif defined(CONFIG_TARGET_T1024RDB)
 145         /* optimize cpo for erratum A-009942 */
 146         popts->cpo_sample = 0x52;
 147 #endif
 148 }
 149
 150 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 151 /* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
 152 dimm_params_t ddr_raw_timing = {
 153         .n_ranks = 1,
 154         .rank_density = 0x80000000,
 155         .capacity = 0x80000000,
 156         .primary_sdram_width = 32,
 157         .ec_sdram_width = 8,
 158         .registered_dimm = 0,
 159         .mirrored_dimm = 0,
 160         .n_row_addr = 15,
 161         .n_col_addr = 10,
 162         .bank_addr_bits = 2,
 163         .bank_group_bits = 2,
 164         .edc_config = 0,
 165         .burst_lengths_bitmask = 0x0c,
 166         .tckmin_x_ps = 938,
 167         .tckmax_ps = 1500,
 168         .caslat_x = 0x000DFA00,
 169         .taa_ps = 13500,
 170         .trcd_ps = 13500,
 171         .trp_ps = 13500,
 172         .tras_ps = 33000,
 173         .trc_ps = 46500,
 174         .trfc1_ps = 260000,
 175         .trfc2_ps = 160000,
 176         .trfc4_ps = 110000,
 177         .tfaw_ps = 25000,
 178         .trrds_ps = 3700,
 179         .trrdl_ps = 5300,
 180         .tccdl_ps = 5355,
 181         .refresh_rate_ps = 7800000,
 182         .dq_mapping[0] = 0x0,
 183         .dq_mapping[1] = 0x0,
 184         .dq_mapping[2] = 0x0,
 185         .dq_mapping[3] = 0x0,
 186         .dq_mapping[4] = 0x0,
 187         .dq_mapping[5] = 0x0,
 188         .dq_mapping[6] = 0x0,
 189         .dq_mapping[7] = 0x0,
 190         .dq_mapping[8] = 0x0,
 191         .dq_mapping[9] = 0x0,
 192         .dq_mapping[10] = 0x0,
 193         .dq_mapping[11] = 0x0,
 194         .dq_mapping[12] = 0x0,
 195         .dq_mapping[13] = 0x0,
 196         .dq_mapping[14] = 0x0,
 197         .dq_mapping[15] = 0x0,
 198         .dq_mapping[16] = 0x0,
 199         .dq_mapping[17] = 0x0,
 200         .dq_mapping_ors = 1,
 201 };
 202
 203 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 204                 unsigned int controller_number,
 205                 unsigned int dimm_number)
 206 {
 207         const char dimm_model[] = "Fixed DDR4 on board";
 208
 209         if (((controller_number == 0) && (dimm_number == 0)) ||
 210             ((controller_number == 1) && (dimm_number == 0))) {
 211                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 212                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 213                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 214         }
 215
 216         return 0;
 217 }
 218 #endif
 219
 220 #if defined(CONFIG_DEEP_SLEEP)
 221 void board_mem_sleep_setup(void)
 222 {
 223         void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
 224
 225         /* does not provide HW signals for power management */
 226         clrbits_8(cpld_base + 0x17, 0x40);
 227         /* Disable MCKE isolation */
 228         gpio_set_value(2, 0);
 229         udelay(1);
 230 }
 231 #endif
 232
 233 int dram_init(void)
 234 {
 235         phys_size_t dram_size;
 236
 237 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 238 #ifndef CONFIG_SYS_DDR_RAW_TIMING
 239         puts("Initializing....using SPD\n");
 240 #endif
 241         dram_size = fsl_ddr_sdram();
 242 #else
 243         /* DDR has been initialised by first stage boot loader */
 244         dram_size =  fsl_ddr_sdram_size();
 245 #endif
 246         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 247         dram_size *= 0x100000;
 248
 249 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 250         fsl_dp_resume();
 251 #endif
 252
 253         gd->ram_size = dram_size;
 254
 255         return 0;
 256 }