board/freescale/t102xqds/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/mmu.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/mpc85xx_gpio.h>
  16 #include <linux/delay.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 struct board_specific_parameters {
  21         u32 n_ranks;
  22         u32 datarate_mhz_high;
  23         u32 rank_gb;
  24         u32 clk_adjust;
  25         u32 wrlvl_start;
  26         u32 wrlvl_ctl_2;
  27         u32 wrlvl_ctl_3;
  28 };
  29
  30 /*
  31  * datarate_mhz_high values need to be in ascending order
  32  */
  33 static const struct board_specific_parameters udimm0[] = {
  34         /*
  35          * memory controller 0
  36          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
  37          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
  38          */
  39 #if defined(CONFIG_SYS_FSL_DDR4)
  40         {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  41         {2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
  42         {1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
  43         {1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
  44         {1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
  45 #elif defined(CONFIG_SYS_FSL_DDR3)
  46         {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  47         {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  48         {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  49         {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  50         {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  51         {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  52 #else
  53 #error DDR type not defined
  54 #endif
  55         {}
  56 };
  57
  58 static const struct board_specific_parameters *udimms[] = {
  59         udimm0,
  60 };
  61
  62 void fsl_ddr_board_options(memctl_options_t *popts,
  63                            dimm_params_t *pdimm,
  64                            unsigned int ctrl_num)
  65 {
  66         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  67         ulong ddr_freq;
  68         struct cpu_type *cpu = gd->arch.cpu;
  69
  70         if (ctrl_num > 2) {
  71                 printf("Not supported controller number %d\n", ctrl_num);
  72                 return;
  73         }
  74         if (!pdimm->n_ranks)
  75                 return;
  76
  77         pbsp = udimms[0];
  78
  79         /* Get clk_adjust according to the board ddr freqency and n_banks
  80          * specified in board_specific_parameters table.
  81          */
  82         ddr_freq = get_ddr_freq(0) / 1000000;
  83         while (pbsp->datarate_mhz_high) {
  84                 if (pbsp->n_ranks == pdimm->n_ranks &&
  85                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  86                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  87                                 popts->clk_adjust = pbsp->clk_adjust;
  88                                 popts->wrlvl_start = pbsp->wrlvl_start;
  89                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  90                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  91                                 goto found;
  92                         }
  93                         pbsp_highest = pbsp;
  94                 }
  95                 pbsp++;
  96         }
  97
  98         if (pbsp_highest) {
  99                 printf("Error: board specific timing not found\n");
 100                 printf("for data rate %lu MT/s\n", ddr_freq);
 101                 printf("Trying to use the highest speed (%u) parameters\n",
 102                        pbsp_highest->datarate_mhz_high);
 103                 popts->clk_adjust = pbsp_highest->clk_adjust;
 104                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
 105                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 106                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
 107         } else {
 108                 panic("DIMM is not supported by this board");
 109         }
 110 found:
 111         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
 112               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
 113         debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
 114               pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
 115         debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
 116
 117         /*
 118          * Factors to consider for half-strength driver enable:
 119          *      - number of DIMMs installed
 120          */
 121         popts->half_strength_driver_enable = 1;
 122         /*
 123          * Write leveling override
 124          */
 125         popts->wrlvl_override = 1;
 126         popts->wrlvl_sample = 0xf;
 127
 128         /*
 129          * rtt and rtt_wr override
 130          */
 131         popts->rtt_override = 0;
 132
 133         /* Enable ZQ calibration */
 134         popts->zq_en = 1;
 135
 136         /* DHC_EN =1, ODT = 75 Ohm */
 137 #ifdef CONFIG_SYS_FSL_DDR4
 138         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 139         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 140                           DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
 141 #else
 142         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 143         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 144
 145         /* optimize cpo for erratum A-009942 */
 146         popts->cpo_sample = 0x5f;
 147 #endif
 148
 149         /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
 150          * set DDR bus width to 32bit for T1023
 151          */
 152         if (cpu->soc_ver == SVR_T1023)
 153                 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 154
 155 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 156         /* for DDR bus 32bit test on T1024 */
 157         popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 158 #endif
 159 }
 160
 161 #if defined(CONFIG_DEEP_SLEEP)
 162 void board_mem_sleep_setup(void)
 163 {
 164         void __iomem *qixis_base = (void *)QIXIS_BASE;
 165
 166         /* does not provide HW signals for power management */
 167         clrbits_8(qixis_base + 0x21, 0x2);
 168         /* Disable MCKE isolation */
 169         gpio_set_value(2, 0);
 170         udelay(1);
 171 }
 172 #endif
 173
 174 int dram_init(void)
 175 {
 176         phys_size_t dram_size;
 177
 178 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 179         puts("Initializing....using SPD\n");
 180         dram_size = fsl_ddr_sdram();
 181 #else
 182         /* DDR has been initialised by first stage boot loader */
 183         dram_size =  fsl_ddr_sdram_size();
 184 #endif
 185         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 186         dram_size *= 0x100000;
 187
 188 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 189         fsl_dp_resume();
 190 #endif
 191
 192         gd->ram_size = dram_size;
 193
 194         return 0;
 195 }