board/freescale/t102xqds/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/mmu.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/mpc85xx_gpio.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 struct board_specific_parameters {
  20         u32 n_ranks;
  21         u32 datarate_mhz_high;
  22         u32 rank_gb;
  23         u32 clk_adjust;
  24         u32 wrlvl_start;
  25         u32 wrlvl_ctl_2;
  26         u32 wrlvl_ctl_3;
  27 };
  28
  29 /*
  30  * datarate_mhz_high values need to be in ascending order
  31  */
  32 static const struct board_specific_parameters udimm0[] = {
  33         /*
  34          * memory controller 0
  35          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
  36          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
  37          */
  38 #if defined(CONFIG_SYS_FSL_DDR4)
  39         {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  40         {2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
  41         {1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
  42         {1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
  43         {1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
  44 #elif defined(CONFIG_SYS_FSL_DDR3)
  45         {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  46         {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  47         {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  48         {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  49         {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  50         {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  51 #else
  52 #error DDR type not defined
  53 #endif
  54         {}
  55 };
  56
  57 static const struct board_specific_parameters *udimms[] = {
  58         udimm0,
  59 };
  60
  61 void fsl_ddr_board_options(memctl_options_t *popts,
  62                            dimm_params_t *pdimm,
  63                            unsigned int ctrl_num)
  64 {
  65         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  66         ulong ddr_freq;
  67         struct cpu_type *cpu = gd->arch.cpu;
  68
  69         if (ctrl_num > 2) {
  70                 printf("Not supported controller number %d\n", ctrl_num);
  71                 return;
  72         }
  73         if (!pdimm->n_ranks)
  74                 return;
  75
  76         pbsp = udimms[0];
  77
  78         /* Get clk_adjust according to the board ddr freqency and n_banks
  79          * specified in board_specific_parameters table.
  80          */
  81         ddr_freq = get_ddr_freq(0) / 1000000;
  82         while (pbsp->datarate_mhz_high) {
  83                 if (pbsp->n_ranks == pdimm->n_ranks &&
  84                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  85                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  86                                 popts->clk_adjust = pbsp->clk_adjust;
  87                                 popts->wrlvl_start = pbsp->wrlvl_start;
  88                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  89                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  90                                 goto found;
  91                         }
  92                         pbsp_highest = pbsp;
  93                 }
  94                 pbsp++;
  95         }
  96
  97         if (pbsp_highest) {
  98                 printf("Error: board specific timing not found\n");
  99                 printf("for data rate %lu MT/s\n", ddr_freq);
 100                 printf("Trying to use the highest speed (%u) parameters\n",
 101                        pbsp_highest->datarate_mhz_high);
 102                 popts->clk_adjust = pbsp_highest->clk_adjust;
 103                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
 104                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 105                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
 106         } else {
 107                 panic("DIMM is not supported by this board");
 108         }
 109 found:
 110         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
 111               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
 112         debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
 113               pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
 114         debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
 115
 116         /*
 117          * Factors to consider for half-strength driver enable:
 118          *      - number of DIMMs installed
 119          */
 120         popts->half_strength_driver_enable = 1;
 121         /*
 122          * Write leveling override
 123          */
 124         popts->wrlvl_override = 1;
 125         popts->wrlvl_sample = 0xf;
 126
 127         /*
 128          * rtt and rtt_wr override
 129          */
 130         popts->rtt_override = 0;
 131
 132         /* Enable ZQ calibration */
 133         popts->zq_en = 1;
 134
 135         /* DHC_EN =1, ODT = 75 Ohm */
 136 #ifdef CONFIG_SYS_FSL_DDR4
 137         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 138         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 139                           DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
 140 #else
 141         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 142         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 143
 144         /* optimize cpo for erratum A-009942 */
 145         popts->cpo_sample = 0x5f;
 146 #endif
 147
 148         /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
 149          * set DDR bus width to 32bit for T1023
 150          */
 151         if (cpu->soc_ver == SVR_T1023)
 152                 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 153
 154 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 155         /* for DDR bus 32bit test on T1024 */
 156         popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 157 #endif
 158 }
 159
 160 #if defined(CONFIG_DEEP_SLEEP)
 161 void board_mem_sleep_setup(void)
 162 {
 163         void __iomem *qixis_base = (void *)QIXIS_BASE;
 164
 165         /* does not provide HW signals for power management */
 166         clrbits_8(qixis_base + 0x21, 0x2);
 167         /* Disable MCKE isolation */
 168         gpio_set_value(2, 0);
 169         udelay(1);
 170 }
 171 #endif
 172
 173 int dram_init(void)
 174 {
 175         phys_size_t dram_size;
 176
 177 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 178         puts("Initializing....using SPD\n");
 179         dram_size = fsl_ddr_sdram();
 180 #else
 181         /* DDR has been initialised by first stage boot loader */
 182         dram_size =  fsl_ddr_sdram_size();
 183 #endif
 184         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 185         dram_size *= 0x100000;
 186
 187 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 188         fsl_dp_resume();
 189 #endif
 190
 191         gd->ram_size = dram_size;
 192
 193         return 0;
 194 }