board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <init.h>
   7 #include <net.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/iomux.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/mx6ul_pins.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/io.h>
  20 #include <common.h>
  21 #include <env.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <linux/delay.h>
  26 #include <linux/sizes.h>
  27 #include <mmc.h>
  28 #include <netdev.h>
  29 #include <power/pmic.h>
  30 #include <power/pfuze3000_pmic.h>
  31 #include "../common/pfuze.h"
  32 #include <usb.h>
  33 #include <usb/ehci-ci.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  38         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  39         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  42         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  43         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  44         PAD_CTL_ODE)
  45
  46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  47         PAD_CTL_SPEED_HIGH   |                                  \
  48         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  49
  50 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  51         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  52
  53 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  54         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  55
  56 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  57
  58 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  59         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  60         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  61
  62 #ifdef CONFIG_DM_PMIC
  63 int power_init_board(void)
  64 {
  65         struct udevice *dev;
  66         int ret, dev_id, rev_id;
  67         unsigned int reg;
  68
  69         ret = pmic_get("pfuze3000", &dev);
  70         if (ret == -ENODEV)
  71                 return 0;
  72         if (ret != 0)
  73                 return ret;
  74
  75         dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  76         rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  77         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  78
  79         /* disable Low Power Mode during standby mode */
  80         reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  81         reg |= 0x1;
  82         pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  83
  84         /* SW1B step ramp up time from 2us to 4us/25mV */
  85         pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
  86
  87         /* SW1B mode to APS/PFM */
  88         pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
  89
  90         /* SW1B standby voltage set to 0.975V */
  91         pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
  92
  93         return 0;
  94 }
  95 #endif
  96
  97 int dram_init(void)
  98 {
  99         gd->ram_size = imx_ddr_size();
 100
 101         return 0;
 102 }
 103
 104 static iomux_v3_cfg_t const uart1_pads[] = {
 105         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 106         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 107 };
 108
 109
 110 static void setup_iomux_uart(void)
 111 {
 112         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 113 }
 114
 115 #ifdef CONFIG_FSL_QSPI
 116 static int board_qspi_init(void)
 117 {
 118         /* Set the clock */
 119         enable_qspi_clk(0);
 120
 121         return 0;
 122 }
 123 #endif
 124
 125 #ifdef CONFIG_SPL_BUILD
 126
 127 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 128         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 129         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 130
 131 static iomux_v3_cfg_t const usdhc2_pads[] = {
 132         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138 };
 139
 140 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 141         {USDHC2_BASE_ADDR, 0, 4},
 142 };
 143
 144 int board_mmc_getcd(struct mmc *mmc)
 145 {
 146         return 1;
 147 }
 148
 149 int board_mmc_init(bd_t *bis)
 150 {
 151         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 152         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 153         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 154 }
 155 #endif
 156
 157 #ifdef CONFIG_USB_EHCI_MX6
 158 #ifndef CONFIG_DM_USB
 159
 160 #define USB_OTHERREGS_OFFSET    0x800
 161 #define UCTRL_PWR_POL           (1 << 9)
 162
 163 static iomux_v3_cfg_t const usb_otg_pads[] = {
 164         MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
 165 };
 166
 167 /* At default the 3v3 enables the MIC2026 for VBUS power */
 168 static void setup_usb(void)
 169 {
 170         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 171                                          ARRAY_SIZE(usb_otg_pads));
 172 }
 173
 174 int board_usb_phy_mode(int port)
 175 {
 176         if (port == 1)
 177                 return USB_INIT_HOST;
 178         else
 179                 return usb_phy_mode(port);
 180 }
 181
 182 int board_ehci_hcd_init(int port)
 183 {
 184         u32 *usbnc_usb_ctrl;
 185
 186         if (port > 1)
 187                 return -EINVAL;
 188
 189         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 190                                  port * 4);
 191
 192         /* Set Power polarity */
 193         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 194
 195         return 0;
 196 }
 197 #endif
 198 #endif
 199
 200 #ifdef CONFIG_FEC_MXC
 201 static int setup_fec(int fec_id)
 202 {
 203         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 204         int ret;
 205
 206         if (fec_id == 0) {
 207                 /*
 208                  * Use 50M anatop loopback REF_CLK1 for ENET1,
 209                  * clear gpr1[13], set gpr1[17].
 210                  */
 211                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 212                                 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 213         } else {
 214                 /*
 215                  * Use 50M anatop loopback REF_CLK2 for ENET2,
 216                  * clear gpr1[14], set gpr1[18].
 217                  */
 218                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 219                                 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 220         }
 221
 222         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 223         if (ret)
 224                 return ret;
 225
 226         enable_enet_clk(1);
 227
 228         return 0;
 229 }
 230
 231 int board_phy_config(struct phy_device *phydev)
 232 {
 233         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
 234
 235         if (phydev->drv->config)
 236                 phydev->drv->config(phydev);
 237
 238         return 0;
 239 }
 240 #endif
 241
 242 #ifdef CONFIG_DM_VIDEO
 243 static iomux_v3_cfg_t const lcd_pads[] = {
 244         /* Use GPIO for Brightness adjustment, duty cycle = period. */
 245         MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 246 };
 247
 248 static int setup_lcd(void)
 249 {
 250         enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
 251
 252         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 253
 254         /* Reset the LCD */
 255         gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
 256         gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
 257         udelay(500);
 258         gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
 259
 260         /* Set Brightness to high */
 261         gpio_request(IMX_GPIO_NR(1, 8), "backlight");
 262         gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
 263
 264         return 0;
 265 }
 266 #else
 267 static inline int setup_lcd(void) { return 0; }
 268 #endif
 269
 270 int board_early_init_f(void)
 271 {
 272         setup_iomux_uart();
 273
 274         return 0;
 275 }
 276
 277 int board_init(void)
 278 {
 279         /* Address of boot parameters */
 280         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 281
 282 #ifdef  CONFIG_FEC_MXC
 283         setup_fec(CONFIG_FEC_ENET_DEV);
 284 #endif
 285
 286 #ifdef CONFIG_USB_EHCI_MX6
 287 #ifndef CONFIG_DM_USB
 288         setup_usb();
 289 #endif
 290 #endif
 291
 292 #ifdef CONFIG_FSL_QSPI
 293         board_qspi_init();
 294 #endif
 295
 296         return 0;
 297 }
 298
 299 #ifdef CONFIG_CMD_BMODE
 300 static const struct boot_mode board_boot_modes[] = {
 301         /* 4 bit bus width */
 302         {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
 303         {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 304         {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
 305         {NULL,   0},
 306 };
 307 #endif
 308
 309 int board_late_init(void)
 310 {
 311 #ifdef CONFIG_CMD_BMODE
 312         add_board_boot_modes(board_boot_modes);
 313 #endif
 314
 315 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 316         env_set("board_name", "EVK");
 317
 318         if (is_mx6ul_9x9_evk())
 319                 env_set("board_rev", "9X9");
 320         else
 321                 env_set("board_rev", "14X14");
 322 #endif
 323
 324         setup_lcd();
 325
 326         return 0;
 327 }
 328
 329 int checkboard(void)
 330 {
 331         if (is_mx6ul_9x9_evk())
 332                 puts("Board: MX6UL 9x9 EVK\n");
 333         else
 334                 puts("Board: MX6UL 14x14 EVK\n");
 335
 336         return 0;
 337 }
 338
 339 /*
 340  * Backlight off and reset LCD before OS handover
 341  */
 342 void board_preboot_os(void)
 343 {
 344         gpio_set_value(IMX_GPIO_NR(1, 8), 0);
 345         gpio_set_value(IMX_GPIO_NR(5, 9), 0);
 346 }
 347
 348 #ifdef CONFIG_SPL_BUILD
 349 #include <linux/libfdt.h>
 350 #include <spl.h>
 351 #include <asm/arch/mx6-ddr.h>
 352
 353
 354 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 355         .grp_addds = 0x00000030,
 356         .grp_ddrmode_ctl = 0x00020000,
 357         .grp_b0ds = 0x00000030,
 358         .grp_ctlds = 0x00000030,
 359         .grp_b1ds = 0x00000030,
 360         .grp_ddrpke = 0x00000000,
 361         .grp_ddrmode = 0x00020000,
 362 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 363         .grp_ddr_type = 0x00080000,
 364 #else
 365         .grp_ddr_type = 0x000c0000,
 366 #endif
 367 };
 368
 369 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 370 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 371         .dram_dqm0 = 0x00000030,
 372         .dram_dqm1 = 0x00000030,
 373         .dram_ras = 0x00000030,
 374         .dram_cas = 0x00000030,
 375         .dram_odt0 = 0x00000000,
 376         .dram_odt1 = 0x00000000,
 377         .dram_sdba2 = 0x00000000,
 378         .dram_sdclk_0 = 0x00000030,
 379         .dram_sdqs0 = 0x00003030,
 380         .dram_sdqs1 = 0x00003030,
 381         .dram_reset = 0x00000030,
 382 };
 383
 384 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 385         .p0_mpwldectrl0 = 0x00000000,
 386         .p0_mpdgctrl0 = 0x20000000,
 387         .p0_mprddlctl = 0x4040484f,
 388         .p0_mpwrdlctl = 0x40405247,
 389         .mpzqlp2ctl = 0x1b4700c7,
 390 };
 391
 392 static struct mx6_lpddr2_cfg mem_ddr = {
 393         .mem_speed = 800,
 394         .density = 2,
 395         .width = 16,
 396         .banks = 4,
 397         .rowaddr = 14,
 398         .coladdr = 10,
 399         .trcd_lp = 1500,
 400         .trppb_lp = 1500,
 401         .trpab_lp = 2000,
 402         .trasmin = 4250,
 403 };
 404
 405 struct mx6_ddr_sysinfo ddr_sysinfo = {
 406         .dsize = 0,
 407         .cs_density = 18,
 408         .ncs = 1,
 409         .cs1_mirror = 0,
 410         .walat = 0,
 411         .ralat = 5,
 412         .mif3_mode = 3,
 413         .bi_on = 1,
 414         .rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
 415         .rtt_nom = 0,
 416         .sde_to_rst = 0,    /* LPDDR2 does not need this field */
 417         .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 418         .ddr_type = DDR_TYPE_LPDDR2,
 419         .refsel = 0,    /* Refresh cycles at 64KHz */
 420         .refr = 3,      /* 4 refresh commands per refresh cycle */
 421 };
 422
 423 #else
 424 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 425         .dram_dqm0 = 0x00000030,
 426         .dram_dqm1 = 0x00000030,
 427         .dram_ras = 0x00000030,
 428         .dram_cas = 0x00000030,
 429         .dram_odt0 = 0x00000030,
 430         .dram_odt1 = 0x00000030,
 431         .dram_sdba2 = 0x00000000,
 432         .dram_sdclk_0 = 0x00000030,
 433         .dram_sdqs0 = 0x00000030,
 434         .dram_sdqs1 = 0x00000030,
 435         .dram_reset = 0x00000030,
 436 };
 437
 438 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 439         .p0_mpwldectrl0 = 0x00000000,
 440         .p0_mpdgctrl0 = 0x41570155,
 441         .p0_mprddlctl = 0x4040474A,
 442         .p0_mpwrdlctl = 0x40405550,
 443 };
 444
 445 struct mx6_ddr_sysinfo ddr_sysinfo = {
 446         .dsize = 0,
 447         .cs_density = 20,
 448         .ncs = 1,
 449         .cs1_mirror = 0,
 450         .rtt_wr = 2,
 451         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 452         .walat = 0,             /* Write additional latency */
 453         .ralat = 5,             /* Read additional latency */
 454         .mif3_mode = 3,         /* Command prediction working mode */
 455         .bi_on = 1,             /* Bank interleaving enabled */
 456         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 457         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 458         .ddr_type = DDR_TYPE_DDR3,
 459         .refsel = 0,    /* Refresh cycles at 64KHz */
 460         .refr = 1,      /* 2 refresh commands per refresh cycle */
 461 };
 462
 463 static struct mx6_ddr3_cfg mem_ddr = {
 464         .mem_speed = 800,
 465         .density = 4,
 466         .width = 16,
 467         .banks = 8,
 468         .rowaddr = 15,
 469         .coladdr = 10,
 470         .pagesz = 2,
 471         .trcd = 1375,
 472         .trcmin = 4875,
 473         .trasmin = 3500,
 474 };
 475 #endif
 476
 477 static void ccgr_init(void)
 478 {
 479         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 480
 481         writel(0xFFFFFFFF, &ccm->CCGR0);
 482         writel(0xFFFFFFFF, &ccm->CCGR1);
 483         writel(0xFFFFFFFF, &ccm->CCGR2);
 484         writel(0xFFFFFFFF, &ccm->CCGR3);
 485         writel(0xFFFFFFFF, &ccm->CCGR4);
 486         writel(0xFFFFFFFF, &ccm->CCGR5);
 487         writel(0xFFFFFFFF, &ccm->CCGR6);
 488         writel(0xFFFFFFFF, &ccm->CCGR7);
 489 }
 490
 491 static void spl_dram_init(void)
 492 {
 493         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 494         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 495 }
 496
 497 void board_init_f(ulong dummy)
 498 {
 499         ccgr_init();
 500
 501         /* setup AIPS and disable watchdog */
 502         arch_cpu_init();
 503
 504         /* iomux and setup of i2c */
 505         board_early_init_f();
 506
 507         /* setup GP timer */
 508         timer_init();
 509
 510         /* UART clocks enabled and gd valid - init serial console */
 511         preloader_console_init();
 512
 513         /* DDR initialization */
 514         spl_dram_init();
 515
 516         /* Clear the BSS. */
 517         memset(__bss_start, 0, __bss_end - __bss_start);
 518
 519         /* load/boot image from boot device */
 520         board_init_r(NULL, 0);
 521 }
 522 #endif