board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <init.h>
   7 #include <net.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/iomux.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/mx6ul_pins.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/io.h>
  20 #include <common.h>
  21 #include <env.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <linux/sizes.h>
  26 #include <mmc.h>
  27 #include <netdev.h>
  28 #include <power/pmic.h>
  29 #include <power/pfuze3000_pmic.h>
  30 #include "../common/pfuze.h"
  31 #include <usb.h>
  32 #include <usb/ehci-ci.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  37         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  38         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  41         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  42         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  43         PAD_CTL_ODE)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  46         PAD_CTL_SPEED_HIGH   |                                  \
  47         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  48
  49 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  50         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  51
  52 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  53         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  54
  55 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  56
  57 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  58         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  59         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #ifdef CONFIG_DM_PMIC
  62 int power_init_board(void)
  63 {
  64         struct udevice *dev;
  65         int ret, dev_id, rev_id;
  66         unsigned int reg;
  67
  68         ret = pmic_get("pfuze3000", &dev);
  69         if (ret == -ENODEV)
  70                 return 0;
  71         if (ret != 0)
  72                 return ret;
  73
  74         dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  75         rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  76         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  77
  78         /* disable Low Power Mode during standby mode */
  79         reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  80         reg |= 0x1;
  81         pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  82
  83         /* SW1B step ramp up time from 2us to 4us/25mV */
  84         pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
  85
  86         /* SW1B mode to APS/PFM */
  87         pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
  88
  89         /* SW1B standby voltage set to 0.975V */
  90         pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
  91
  92         return 0;
  93 }
  94 #endif
  95
  96 int dram_init(void)
  97 {
  98         gd->ram_size = imx_ddr_size();
  99
 100         return 0;
 101 }
 102
 103 static iomux_v3_cfg_t const uart1_pads[] = {
 104         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 105         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 106 };
 107
 108
 109 static void setup_iomux_uart(void)
 110 {
 111         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 112 }
 113
 114 #ifdef CONFIG_FSL_QSPI
 115 static int board_qspi_init(void)
 116 {
 117         /* Set the clock */
 118         enable_qspi_clk(0);
 119
 120         return 0;
 121 }
 122 #endif
 123
 124 #ifdef CONFIG_SPL_BUILD
 125
 126 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 127         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 128         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 129
 130 static iomux_v3_cfg_t const usdhc2_pads[] = {
 131         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137 };
 138
 139 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 140         {USDHC2_BASE_ADDR, 0, 4},
 141 };
 142
 143 int board_mmc_getcd(struct mmc *mmc)
 144 {
 145         return 1;
 146 }
 147
 148 int board_mmc_init(bd_t *bis)
 149 {
 150         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 151         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 152         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 153 }
 154 #endif
 155
 156 #ifdef CONFIG_USB_EHCI_MX6
 157 #ifndef CONFIG_DM_USB
 158
 159 #define USB_OTHERREGS_OFFSET    0x800
 160 #define UCTRL_PWR_POL           (1 << 9)
 161
 162 static iomux_v3_cfg_t const usb_otg_pads[] = {
 163         MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
 164 };
 165
 166 /* At default the 3v3 enables the MIC2026 for VBUS power */
 167 static void setup_usb(void)
 168 {
 169         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 170                                          ARRAY_SIZE(usb_otg_pads));
 171 }
 172
 173 int board_usb_phy_mode(int port)
 174 {
 175         if (port == 1)
 176                 return USB_INIT_HOST;
 177         else
 178                 return usb_phy_mode(port);
 179 }
 180
 181 int board_ehci_hcd_init(int port)
 182 {
 183         u32 *usbnc_usb_ctrl;
 184
 185         if (port > 1)
 186                 return -EINVAL;
 187
 188         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 189                                  port * 4);
 190
 191         /* Set Power polarity */
 192         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 193
 194         return 0;
 195 }
 196 #endif
 197 #endif
 198
 199 #ifdef CONFIG_FEC_MXC
 200 static int setup_fec(int fec_id)
 201 {
 202         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 203         int ret;
 204
 205         if (fec_id == 0) {
 206                 /*
 207                  * Use 50M anatop loopback REF_CLK1 for ENET1,
 208                  * clear gpr1[13], set gpr1[17].
 209                  */
 210                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 211                                 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 212         } else {
 213                 /*
 214                  * Use 50M anatop loopback REF_CLK2 for ENET2,
 215                  * clear gpr1[14], set gpr1[18].
 216                  */
 217                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 218                                 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 219         }
 220
 221         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 222         if (ret)
 223                 return ret;
 224
 225         enable_enet_clk(1);
 226
 227         return 0;
 228 }
 229
 230 int board_phy_config(struct phy_device *phydev)
 231 {
 232         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
 233
 234         if (phydev->drv->config)
 235                 phydev->drv->config(phydev);
 236
 237         return 0;
 238 }
 239 #endif
 240
 241 #ifdef CONFIG_DM_VIDEO
 242 static iomux_v3_cfg_t const lcd_pads[] = {
 243         /* Use GPIO for Brightness adjustment, duty cycle = period. */
 244         MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 245 };
 246
 247 static int setup_lcd(void)
 248 {
 249         enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
 250
 251         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 252
 253         /* Reset the LCD */
 254         gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
 255         gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
 256         udelay(500);
 257         gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
 258
 259         /* Set Brightness to high */
 260         gpio_request(IMX_GPIO_NR(1, 8), "backlight");
 261         gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
 262
 263         return 0;
 264 }
 265 #else
 266 static inline int setup_lcd(void) { return 0; }
 267 #endif
 268
 269 int board_early_init_f(void)
 270 {
 271         setup_iomux_uart();
 272
 273         return 0;
 274 }
 275
 276 int board_init(void)
 277 {
 278         /* Address of boot parameters */
 279         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 280
 281 #ifdef  CONFIG_FEC_MXC
 282         setup_fec(CONFIG_FEC_ENET_DEV);
 283 #endif
 284
 285 #ifdef CONFIG_USB_EHCI_MX6
 286 #ifndef CONFIG_DM_USB
 287         setup_usb();
 288 #endif
 289 #endif
 290
 291 #ifdef CONFIG_FSL_QSPI
 292         board_qspi_init();
 293 #endif
 294
 295         return 0;
 296 }
 297
 298 #ifdef CONFIG_CMD_BMODE
 299 static const struct boot_mode board_boot_modes[] = {
 300         /* 4 bit bus width */
 301         {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
 302         {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 303         {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
 304         {NULL,   0},
 305 };
 306 #endif
 307
 308 int board_late_init(void)
 309 {
 310 #ifdef CONFIG_CMD_BMODE
 311         add_board_boot_modes(board_boot_modes);
 312 #endif
 313
 314 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 315         env_set("board_name", "EVK");
 316
 317         if (is_mx6ul_9x9_evk())
 318                 env_set("board_rev", "9X9");
 319         else
 320                 env_set("board_rev", "14X14");
 321 #endif
 322
 323         setup_lcd();
 324
 325         return 0;
 326 }
 327
 328 int checkboard(void)
 329 {
 330         if (is_mx6ul_9x9_evk())
 331                 puts("Board: MX6UL 9x9 EVK\n");
 332         else
 333                 puts("Board: MX6UL 14x14 EVK\n");
 334
 335         return 0;
 336 }
 337
 338 /*
 339  * Backlight off and reset LCD before OS handover
 340  */
 341 void board_preboot_os(void)
 342 {
 343         gpio_set_value(IMX_GPIO_NR(1, 8), 0);
 344         gpio_set_value(IMX_GPIO_NR(5, 9), 0);
 345 }
 346
 347 #ifdef CONFIG_SPL_BUILD
 348 #include <linux/libfdt.h>
 349 #include <spl.h>
 350 #include <asm/arch/mx6-ddr.h>
 351
 352
 353 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 354         .grp_addds = 0x00000030,
 355         .grp_ddrmode_ctl = 0x00020000,
 356         .grp_b0ds = 0x00000030,
 357         .grp_ctlds = 0x00000030,
 358         .grp_b1ds = 0x00000030,
 359         .grp_ddrpke = 0x00000000,
 360         .grp_ddrmode = 0x00020000,
 361 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 362         .grp_ddr_type = 0x00080000,
 363 #else
 364         .grp_ddr_type = 0x000c0000,
 365 #endif
 366 };
 367
 368 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 369 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 370         .dram_dqm0 = 0x00000030,
 371         .dram_dqm1 = 0x00000030,
 372         .dram_ras = 0x00000030,
 373         .dram_cas = 0x00000030,
 374         .dram_odt0 = 0x00000000,
 375         .dram_odt1 = 0x00000000,
 376         .dram_sdba2 = 0x00000000,
 377         .dram_sdclk_0 = 0x00000030,
 378         .dram_sdqs0 = 0x00003030,
 379         .dram_sdqs1 = 0x00003030,
 380         .dram_reset = 0x00000030,
 381 };
 382
 383 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 384         .p0_mpwldectrl0 = 0x00000000,
 385         .p0_mpdgctrl0 = 0x20000000,
 386         .p0_mprddlctl = 0x4040484f,
 387         .p0_mpwrdlctl = 0x40405247,
 388         .mpzqlp2ctl = 0x1b4700c7,
 389 };
 390
 391 static struct mx6_lpddr2_cfg mem_ddr = {
 392         .mem_speed = 800,
 393         .density = 2,
 394         .width = 16,
 395         .banks = 4,
 396         .rowaddr = 14,
 397         .coladdr = 10,
 398         .trcd_lp = 1500,
 399         .trppb_lp = 1500,
 400         .trpab_lp = 2000,
 401         .trasmin = 4250,
 402 };
 403
 404 struct mx6_ddr_sysinfo ddr_sysinfo = {
 405         .dsize = 0,
 406         .cs_density = 18,
 407         .ncs = 1,
 408         .cs1_mirror = 0,
 409         .walat = 0,
 410         .ralat = 5,
 411         .mif3_mode = 3,
 412         .bi_on = 1,
 413         .rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
 414         .rtt_nom = 0,
 415         .sde_to_rst = 0,    /* LPDDR2 does not need this field */
 416         .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 417         .ddr_type = DDR_TYPE_LPDDR2,
 418         .refsel = 0,    /* Refresh cycles at 64KHz */
 419         .refr = 3,      /* 4 refresh commands per refresh cycle */
 420 };
 421
 422 #else
 423 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 424         .dram_dqm0 = 0x00000030,
 425         .dram_dqm1 = 0x00000030,
 426         .dram_ras = 0x00000030,
 427         .dram_cas = 0x00000030,
 428         .dram_odt0 = 0x00000030,
 429         .dram_odt1 = 0x00000030,
 430         .dram_sdba2 = 0x00000000,
 431         .dram_sdclk_0 = 0x00000030,
 432         .dram_sdqs0 = 0x00000030,
 433         .dram_sdqs1 = 0x00000030,
 434         .dram_reset = 0x00000030,
 435 };
 436
 437 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 438         .p0_mpwldectrl0 = 0x00000000,
 439         .p0_mpdgctrl0 = 0x41570155,
 440         .p0_mprddlctl = 0x4040474A,
 441         .p0_mpwrdlctl = 0x40405550,
 442 };
 443
 444 struct mx6_ddr_sysinfo ddr_sysinfo = {
 445         .dsize = 0,
 446         .cs_density = 20,
 447         .ncs = 1,
 448         .cs1_mirror = 0,
 449         .rtt_wr = 2,
 450         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 451         .walat = 0,             /* Write additional latency */
 452         .ralat = 5,             /* Read additional latency */
 453         .mif3_mode = 3,         /* Command prediction working mode */
 454         .bi_on = 1,             /* Bank interleaving enabled */
 455         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 456         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 457         .ddr_type = DDR_TYPE_DDR3,
 458         .refsel = 0,    /* Refresh cycles at 64KHz */
 459         .refr = 1,      /* 2 refresh commands per refresh cycle */
 460 };
 461
 462 static struct mx6_ddr3_cfg mem_ddr = {
 463         .mem_speed = 800,
 464         .density = 4,
 465         .width = 16,
 466         .banks = 8,
 467         .rowaddr = 15,
 468         .coladdr = 10,
 469         .pagesz = 2,
 470         .trcd = 1375,
 471         .trcmin = 4875,
 472         .trasmin = 3500,
 473 };
 474 #endif
 475
 476 static void ccgr_init(void)
 477 {
 478         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 479
 480         writel(0xFFFFFFFF, &ccm->CCGR0);
 481         writel(0xFFFFFFFF, &ccm->CCGR1);
 482         writel(0xFFFFFFFF, &ccm->CCGR2);
 483         writel(0xFFFFFFFF, &ccm->CCGR3);
 484         writel(0xFFFFFFFF, &ccm->CCGR4);
 485         writel(0xFFFFFFFF, &ccm->CCGR5);
 486         writel(0xFFFFFFFF, &ccm->CCGR6);
 487         writel(0xFFFFFFFF, &ccm->CCGR7);
 488 }
 489
 490 static void spl_dram_init(void)
 491 {
 492         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 493         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 494 }
 495
 496 void board_init_f(ulong dummy)
 497 {
 498         ccgr_init();
 499
 500         /* setup AIPS and disable watchdog */
 501         arch_cpu_init();
 502
 503         /* iomux and setup of i2c */
 504         board_early_init_f();
 505
 506         /* setup GP timer */
 507         timer_init();
 508
 509         /* UART clocks enabled and gd valid - init serial console */
 510         preloader_console_init();
 511
 512         /* DDR initialization */
 513         spl_dram_init();
 514
 515         /* Clear the BSS. */
 516         memset(__bss_start, 0, __bss_end - __bss_start);
 517
 518         /* load/boot image from boot device */
 519         board_init_r(NULL, 0);
 520 }
 521 #endif