board/freescale/mx6sxsabreauto/mx6sxsabreauto.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Ye Li <ye.li@nxp.com>
   6  */
   7
   8 #include <init.h>
   9 #include <net.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/io.h>
  20 #include <linux/delay.h>
  21 #include <linux/sizes.h>
  22 #include <common.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <power/pmic.h>
  27 #include <power/pfuze100_pmic.h>
  28 #include "../common/pfuze.h"
  29 #include <usb.h>
  30 #include <usb/ehci-ci.h>
  31 #include <pca953x.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  36         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  37         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  40         PAD_CTL_SPEED_HIGH   |                                   \
  41         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  42
  43 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  44         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  45
  46 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  47         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  48
  49 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  50 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  51                         PAD_CTL_SRE_FAST)
  52 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  53
  54 int dram_init(void)
  55 {
  56         gd->ram_size = imx_ddr_size();
  57
  58         return 0;
  59 }
  60
  61 static iomux_v3_cfg_t const uart1_pads[] = {
  62         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  64 };
  65
  66 static iomux_v3_cfg_t const fec2_pads[] = {
  67         MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  70         MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  71         MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  72         MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  73         MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  74         MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  75         MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81 };
  82
  83 static void setup_iomux_uart(void)
  84 {
  85         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  86 }
  87
  88 static int setup_fec(void)
  89 {
  90         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  91
  92         /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
  93         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
  94
  95         return enable_fec_anatop_clock(1, ENET_125MHZ);
  96 }
  97
  98 int board_eth_init(bd_t *bis)
  99 {
 100         int ret;
 101
 102         imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
 103         setup_fec();
 104
 105         ret = fecmxc_initialize_multi(bis, 1,
 106                 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 107         if (ret)
 108                 printf("FEC%d MXC: %s:failed\n", 1, __func__);
 109
 110         return ret;
 111 }
 112
 113 int board_phy_config(struct phy_device *phydev)
 114 {
 115         /*
 116          * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
 117          * Phy control debug reg 0
 118          */
 119         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 120         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 121
 122         /* rgmii tx clock delay enable */
 123         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 124         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 125
 126         if (phydev->drv->config)
 127                 phydev->drv->config(phydev);
 128
 129         return 0;
 130 }
 131
 132 int power_init_board(void)
 133 {
 134         struct udevice *dev;
 135         int ret;
 136         u32 dev_id, rev_id, i;
 137         u32 switch_num = 6;
 138         u32 offset = PFUZE100_SW1CMODE;
 139
 140         ret = pmic_get("pfuze100", &dev);
 141         if (ret == -ENODEV)
 142                 return 0;
 143
 144         if (ret != 0)
 145                 return ret;
 146
 147         dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
 148         rev_id = pmic_reg_read(dev, PFUZE100_REVID);
 149         printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 150
 151
 152         /* Init mode to APS_PFM */
 153         pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
 154
 155         for (i = 0; i < switch_num - 1; i++)
 156                 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
 157
 158         /* set SW1AB staby volatage 0.975V */
 159         pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
 160
 161         /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 162         pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
 163
 164         /* set SW1C staby volatage 1.10V */
 165         pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
 166
 167         /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 168         pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
 169
 170         return 0;
 171 }
 172
 173 #ifdef CONFIG_USB_EHCI_MX6
 174 #define USB_OTHERREGS_OFFSET    0x800
 175 #define UCTRL_PWR_POL           (1 << 9)
 176
 177 static iomux_v3_cfg_t const usb_otg_pads[] = {
 178         /* OGT1 */
 179         MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 180         MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 181         /* OTG2 */
 182         MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 183 };
 184
 185 static void setup_usb(void)
 186 {
 187         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 188                                          ARRAY_SIZE(usb_otg_pads));
 189 }
 190
 191 int board_usb_phy_mode(int port)
 192 {
 193         if (port == 1)
 194                 return USB_INIT_HOST;
 195         else
 196                 return usb_phy_mode(port);
 197 }
 198
 199 int board_ehci_hcd_init(int port)
 200 {
 201         u32 *usbnc_usb_ctrl;
 202
 203         if (port > 1)
 204                 return -EINVAL;
 205
 206         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 207                                  port * 4);
 208
 209         /* Set Power polarity */
 210         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 211
 212         return 0;
 213 }
 214 #endif
 215
 216 int board_early_init_f(void)
 217 {
 218         setup_iomux_uart();
 219
 220         return 0;
 221 }
 222
 223 #ifdef CONFIG_FSL_QSPI
 224 int board_qspi_init(void)
 225 {
 226         /* Set the clock */
 227         enable_qspi_clk(0);
 228
 229         return 0;
 230 }
 231 #endif
 232
 233 #ifdef CONFIG_NAND_MXS
 234 iomux_v3_cfg_t gpmi_pads[] = {
 235         MX6_PAD_NAND_CLE__RAWNAND_CLE           | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 236         MX6_PAD_NAND_ALE__RAWNAND_ALE           | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 237         MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 238         MX6_PAD_NAND_READY_B__RAWNAND_READY_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
 239         MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B               | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 240         MX6_PAD_NAND_RE_B__RAWNAND_RE_B         | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 241         MX6_PAD_NAND_WE_B__RAWNAND_WE_B         | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 242         MX6_PAD_NAND_DATA00__RAWNAND_DATA00     | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 243         MX6_PAD_NAND_DATA01__RAWNAND_DATA01     | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 244         MX6_PAD_NAND_DATA02__RAWNAND_DATA02     | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 245         MX6_PAD_NAND_DATA03__RAWNAND_DATA03     | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 246         MX6_PAD_NAND_DATA04__RAWNAND_DATA04     | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 247         MX6_PAD_NAND_DATA05__RAWNAND_DATA05     | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 248         MX6_PAD_NAND_DATA06__RAWNAND_DATA06     | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 249         MX6_PAD_NAND_DATA07__RAWNAND_DATA07     | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 250 };
 251
 252 static void setup_gpmi_nand(void)
 253 {
 254         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 255
 256         /* config gpmi nand iomux */
 257         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 258
 259         setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
 260                         MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
 261                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
 262
 263         /* enable apbh clock gating */
 264         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 265 }
 266 #endif
 267
 268 int board_init(void)
 269 {
 270         struct gpio_desc desc;
 271         int ret;
 272
 273         /* Address of boot parameters */
 274         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 275
 276         ret = dm_gpio_lookup_name("gpio@30_4", &desc);
 277         if (ret)
 278                 return ret;
 279
 280         ret = dm_gpio_request(&desc, "cpu_per_rst_b");
 281         if (ret)
 282                 return ret;
 283         /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
 284         dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
 285         udelay(500);
 286         dm_gpio_set_value(&desc, 1);
 287
 288         ret = dm_gpio_lookup_name("gpio@32_2", &desc);
 289         if (ret)
 290                 return ret;
 291
 292         ret = dm_gpio_request(&desc, "steer_enet");
 293         if (ret)
 294                 return ret;
 295
 296         dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
 297         udelay(500);
 298         /* Set steering signal to L for selecting B0 */
 299         dm_gpio_set_value(&desc, 0);
 300
 301 #ifdef CONFIG_USB_EHCI_MX6
 302         setup_usb();
 303 #endif
 304
 305 #ifdef CONFIG_FSL_QSPI
 306         board_qspi_init();
 307 #endif
 308
 309 #ifdef CONFIG_NAND_MXS
 310         setup_gpmi_nand();
 311 #endif
 312
 313         return 0;
 314 }
 315
 316 #ifdef CONFIG_CMD_BMODE
 317 static const struct boot_mode board_boot_modes[] = {
 318         {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
 319         {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 320         {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
 321         {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
 322         {NULL,   0},
 323 };
 324 #endif
 325
 326 int board_late_init(void)
 327 {
 328 #ifdef CONFIG_CMD_BMODE
 329         add_board_boot_modes(board_boot_modes);
 330 #endif
 331
 332         return 0;
 333 }
 334
 335 int checkboard(void)
 336 {
 337         puts("Board: MX6SX SABRE AUTO\n");
 338
 339         return 0;
 340 }