board/freescale/mx6sabresd/mx6sabresd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <asm/mach-imx/spi.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/mxc_i2c.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <input.h>
  29 #include <power/pmic.h>
  30 #include <power/pfuze100_pmic.h>
  31 #include "../common/pfuze.h"
  32 #include <usb.h>
  33 #include <usb/ehci-ci.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  42         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  49                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  50
  51 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54
  55 #define I2C_PMIC        1
  56
  57 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  58
  59 #define DISP0_PWR_EN    IMX_GPIO_NR(1, 21)
  60
  61 #define KEY_VOL_UP      IMX_GPIO_NR(1, 4)
  62
  63 int dram_init(void)
  64 {
  65         gd->ram_size = imx_ddr_size();
  66         return 0;
  67 }
  68
  69 static iomux_v3_cfg_t const uart1_pads[] = {
  70         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  71         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  72 };
  73
  74 static iomux_v3_cfg_t const enet_pads[] = {
  75         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK        | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90         /* AR8031 PHY Reset */
  91         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92 };
  93
  94 static void setup_iomux_enet(void)
  95 {
  96         SETUP_IOMUX_PADS(enet_pads);
  97
  98         /* Reset AR8031 PHY */
  99         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
 100         mdelay(10);
 101         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 102         udelay(100);
 103 }
 104
 105 static iomux_v3_cfg_t const usdhc2_pads[] = {
 106         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 107         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 108         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 109         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 110         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 111         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 112         IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 113         IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 114         IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 115         IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 116         IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02     | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 117 };
 118
 119 static iomux_v3_cfg_t const usdhc3_pads[] = {
 120         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 121         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 122         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 123         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 129         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 130         IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 131 };
 132
 133 static iomux_v3_cfg_t const usdhc4_pads[] = {
 134         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 143         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 144 };
 145
 146 static iomux_v3_cfg_t const ecspi1_pads[] = {
 147         IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 148         IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 149         IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 150         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 151 };
 152
 153 static iomux_v3_cfg_t const rgb_pads[] = {
 154         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
 155         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 156         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 157         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 158         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 159         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 160         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 161         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 162         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 163         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 164         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 165         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 166         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 167         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 168         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 169         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 170         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 171         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 172         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 173         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 174         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 175         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 176         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 177         IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 178         IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 179         IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 180         IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 181         IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 182         IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 183 };
 184
 185 static iomux_v3_cfg_t const bl_pads[] = {
 186         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 187 };
 188
 189 static void enable_backlight(void)
 190 {
 191         SETUP_IOMUX_PADS(bl_pads);
 192         gpio_direction_output(DISP0_PWR_EN, 1);
 193 }
 194
 195 static void enable_rgb(struct display_info_t const *dev)
 196 {
 197         SETUP_IOMUX_PADS(rgb_pads);
 198         enable_backlight();
 199 }
 200
 201 static void enable_lvds(struct display_info_t const *dev)
 202 {
 203         enable_backlight();
 204 }
 205
 206 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
 207         .scl = {
 208                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 209                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 210                 .gp = IMX_GPIO_NR(4, 12)
 211         },
 212         .sda = {
 213                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 214                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 215                 .gp = IMX_GPIO_NR(4, 13)
 216         }
 217 };
 218
 219 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 220         .scl = {
 221                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 222                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 223                 .gp = IMX_GPIO_NR(4, 12)
 224         },
 225         .sda = {
 226                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 227                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 228                 .gp = IMX_GPIO_NR(4, 13)
 229         }
 230 };
 231
 232 static void setup_spi(void)
 233 {
 234         SETUP_IOMUX_PADS(ecspi1_pads);
 235 }
 236
 237 iomux_v3_cfg_t const pcie_pads[] = {
 238         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),        /* POWER */
 239         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),        /* RESET */
 240 };
 241
 242 static void setup_pcie(void)
 243 {
 244         SETUP_IOMUX_PADS(pcie_pads);
 245 }
 246
 247 iomux_v3_cfg_t const di0_pads[] = {
 248         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),        /* DISP0_CLK */
 249         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),               /* DISP0_HSYNC */
 250         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),               /* DISP0_VSYNC */
 251 };
 252
 253 static void setup_iomux_uart(void)
 254 {
 255         SETUP_IOMUX_PADS(uart1_pads);
 256 }
 257
 258 #ifdef CONFIG_FSL_ESDHC
 259 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 260         {USDHC2_BASE_ADDR},
 261         {USDHC3_BASE_ADDR},
 262         {USDHC4_BASE_ADDR},
 263 };
 264
 265 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 266 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 267
 268 int board_mmc_get_env_dev(int devno)
 269 {
 270         return devno - 1;
 271 }
 272
 273 int board_mmc_getcd(struct mmc *mmc)
 274 {
 275         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 276         int ret = 0;
 277
 278         switch (cfg->esdhc_base) {
 279         case USDHC2_BASE_ADDR:
 280                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 281                 break;
 282         case USDHC3_BASE_ADDR:
 283                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 284                 break;
 285         case USDHC4_BASE_ADDR:
 286                 ret = 1; /* eMMC/uSDHC4 is always present */
 287                 break;
 288         }
 289
 290         return ret;
 291 }
 292
 293 int board_mmc_init(bd_t *bis)
 294 {
 295 #ifndef CONFIG_SPL_BUILD
 296         int ret;
 297         int i;
 298
 299         /*
 300          * According to the board_mmc_init() the following map is done:
 301          * (U-Boot device node)    (Physical Port)
 302          * mmc0                    SD2
 303          * mmc1                    SD3
 304          * mmc2                    eMMC
 305          */
 306         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 307                 switch (i) {
 308                 case 0:
 309                         SETUP_IOMUX_PADS(usdhc2_pads);
 310                         gpio_direction_input(USDHC2_CD_GPIO);
 311                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 312                         break;
 313                 case 1:
 314                         SETUP_IOMUX_PADS(usdhc3_pads);
 315                         gpio_direction_input(USDHC3_CD_GPIO);
 316                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 317                         break;
 318                 case 2:
 319                         SETUP_IOMUX_PADS(usdhc4_pads);
 320                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 321                         break;
 322                 default:
 323                         printf("Warning: you configured more USDHC controllers"
 324                                "(%d) then supported by the board (%d)\n",
 325                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 326                         return -EINVAL;
 327                 }
 328
 329                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 330                 if (ret)
 331                         return ret;
 332         }
 333
 334         return 0;
 335 #else
 336         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 337         unsigned reg = readl(&psrc->sbmr1) >> 11;
 338         /*
 339          * Upon reading BOOT_CFG register the following map is done:
 340          * Bit 11 and 12 of BOOT_CFG register can determine the current
 341          * mmc port
 342          * 0x1                  SD1
 343          * 0x2                  SD2
 344          * 0x3                  SD4
 345          */
 346
 347         switch (reg & 0x3) {
 348         case 0x1:
 349                 SETUP_IOMUX_PADS(usdhc2_pads);
 350                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 351                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 352                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 353                 break;
 354         case 0x2:
 355                 SETUP_IOMUX_PADS(usdhc3_pads);
 356                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 357                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 358                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 359                 break;
 360         case 0x3:
 361                 SETUP_IOMUX_PADS(usdhc4_pads);
 362                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 363                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 364                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 365                 break;
 366         }
 367
 368         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 369 #endif
 370 }
 371 #endif
 372
 373 static int ar8031_phy_fixup(struct phy_device *phydev)
 374 {
 375         unsigned short val;
 376
 377         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 378         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 379         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 380         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 381
 382         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 383         val &= 0xffe3;
 384         val |= 0x18;
 385         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 386
 387         /* introduce tx clock delay */
 388         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 389         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 390         val |= 0x0100;
 391         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 392
 393         return 0;
 394 }
 395
 396 int board_phy_config(struct phy_device *phydev)
 397 {
 398         ar8031_phy_fixup(phydev);
 399
 400         if (phydev->drv->config)
 401                 phydev->drv->config(phydev);
 402
 403         return 0;
 404 }
 405
 406 #if defined(CONFIG_VIDEO_IPUV3)
 407 static void disable_lvds(struct display_info_t const *dev)
 408 {
 409         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 410
 411         int reg = readl(&iomux->gpr[2]);
 412
 413         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 414                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 415
 416         writel(reg, &iomux->gpr[2]);
 417 }
 418
 419 static void do_enable_hdmi(struct display_info_t const *dev)
 420 {
 421         disable_lvds(dev);
 422         imx_enable_hdmi_phy();
 423 }
 424
 425 struct display_info_t const displays[] = {{
 426         .bus    = -1,
 427         .addr   = 0,
 428         .pixfmt = IPU_PIX_FMT_RGB666,
 429         .detect = NULL,
 430         .enable = enable_lvds,
 431         .mode   = {
 432                 .name           = "Hannstar-XGA",
 433                 .refresh        = 60,
 434                 .xres           = 1024,
 435                 .yres           = 768,
 436                 .pixclock       = 15384,
 437                 .left_margin    = 160,
 438                 .right_margin   = 24,
 439                 .upper_margin   = 29,
 440                 .lower_margin   = 3,
 441                 .hsync_len      = 136,
 442                 .vsync_len      = 6,
 443                 .sync           = FB_SYNC_EXT,
 444                 .vmode          = FB_VMODE_NONINTERLACED
 445 } }, {
 446         .bus    = -1,
 447         .addr   = 0,
 448         .pixfmt = IPU_PIX_FMT_RGB24,
 449         .detect = detect_hdmi,
 450         .enable = do_enable_hdmi,
 451         .mode   = {
 452                 .name           = "HDMI",
 453                 .refresh        = 60,
 454                 .xres           = 1024,
 455                 .yres           = 768,
 456                 .pixclock       = 15384,
 457                 .left_margin    = 160,
 458                 .right_margin   = 24,
 459                 .upper_margin   = 29,
 460                 .lower_margin   = 3,
 461                 .hsync_len      = 136,
 462                 .vsync_len      = 6,
 463                 .sync           = FB_SYNC_EXT,
 464                 .vmode          = FB_VMODE_NONINTERLACED
 465 } }, {
 466         .bus    = 0,
 467         .addr   = 0,
 468         .pixfmt = IPU_PIX_FMT_RGB24,
 469         .detect = NULL,
 470         .enable = enable_rgb,
 471         .mode   = {
 472                 .name           = "SEIKO-WVGA",
 473                 .refresh        = 60,
 474                 .xres           = 800,
 475                 .yres           = 480,
 476                 .pixclock       = 29850,
 477                 .left_margin    = 89,
 478                 .right_margin   = 164,
 479                 .upper_margin   = 23,
 480                 .lower_margin   = 10,
 481                 .hsync_len      = 10,
 482                 .vsync_len      = 10,
 483                 .sync           = 0,
 484                 .vmode          = FB_VMODE_NONINTERLACED
 485 } } };
 486 size_t display_count = ARRAY_SIZE(displays);
 487
 488 static void setup_display(void)
 489 {
 490         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 491         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 492         int reg;
 493
 494         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 495         SETUP_IOMUX_PADS(di0_pads);
 496
 497         enable_ipu_clock();
 498         imx_setup_hdmi();
 499
 500         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 501         reg = readl(&mxc_ccm->CCGR3);
 502         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 503         writel(reg, &mxc_ccm->CCGR3);
 504
 505         /* set LDB0, LDB1 clk select to 011/011 */
 506         reg = readl(&mxc_ccm->cs2cdr);
 507         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 508                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 509         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 510               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 511         writel(reg, &mxc_ccm->cs2cdr);
 512
 513         reg = readl(&mxc_ccm->cscmr2);
 514         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 515         writel(reg, &mxc_ccm->cscmr2);
 516
 517         reg = readl(&mxc_ccm->chsccdr);
 518         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 519                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 520         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 521                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 522         writel(reg, &mxc_ccm->chsccdr);
 523
 524         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 525              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 526              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 527              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 528              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 529              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 530              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 531              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 532              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 533         writel(reg, &iomux->gpr[2]);
 534
 535         reg = readl(&iomux->gpr[3]);
 536         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 537                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 538             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 539                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 540         writel(reg, &iomux->gpr[3]);
 541 }
 542 #endif /* CONFIG_VIDEO_IPUV3 */
 543
 544 /*
 545  * Do not overwrite the console
 546  * Use always serial for U-Boot console
 547  */
 548 int overwrite_console(void)
 549 {
 550         return 1;
 551 }
 552
 553 int board_eth_init(bd_t *bis)
 554 {
 555         setup_iomux_enet();
 556         setup_pcie();
 557
 558         return cpu_eth_init(bis);
 559 }
 560
 561 #ifdef CONFIG_USB_EHCI_MX6
 562 #define USB_OTHERREGS_OFFSET    0x800
 563 #define UCTRL_PWR_POL           (1 << 9)
 564
 565 static iomux_v3_cfg_t const usb_otg_pads[] = {
 566         IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
 567         IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
 568 };
 569
 570 static iomux_v3_cfg_t const usb_hc1_pads[] = {
 571         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 572 };
 573
 574 static void setup_usb(void)
 575 {
 576         SETUP_IOMUX_PADS(usb_otg_pads);
 577
 578         /*
 579          * set daisy chain for otg_pin_id on 6q.
 580          * for 6dl, this bit is reserved
 581          */
 582         imx_iomux_set_gpr_register(1, 13, 1, 0);
 583
 584         SETUP_IOMUX_PADS(usb_hc1_pads);
 585 }
 586
 587 int board_ehci_hcd_init(int port)
 588 {
 589         u32 *usbnc_usb_ctrl;
 590
 591         if (port > 1)
 592                 return -EINVAL;
 593
 594         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 595                                  port * 4);
 596
 597         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 598
 599         return 0;
 600 }
 601
 602 int board_ehci_power(int port, int on)
 603 {
 604         switch (port) {
 605         case 0:
 606                 break;
 607         case 1:
 608                 if (on)
 609                         gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
 610                 else
 611                         gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
 612                 break;
 613         default:
 614                 printf("MXC USB port %d not yet supported\n", port);
 615                 return -EINVAL;
 616         }
 617
 618         return 0;
 619 }
 620 #endif
 621
 622 int board_early_init_f(void)
 623 {
 624         setup_iomux_uart();
 625
 626         return 0;
 627 }
 628
 629 int board_init(void)
 630 {
 631         /* address of boot parameters */
 632         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 633
 634 #ifdef CONFIG_MXC_SPI
 635         setup_spi();
 636 #endif
 637         if (is_mx6dq() || is_mx6dqp())
 638                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 639         else
 640                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 641 #if defined(CONFIG_VIDEO_IPUV3)
 642         setup_display();
 643 #endif
 644 #ifdef CONFIG_USB_EHCI_MX6
 645         setup_usb();
 646 #endif
 647
 648         return 0;
 649 }
 650
 651 int power_init_board(void)
 652 {
 653         struct pmic *p;
 654         unsigned int reg;
 655         int ret;
 656
 657         p = pfuze_common_init(I2C_PMIC);
 658         if (!p)
 659                 return -ENODEV;
 660
 661         ret = pfuze_mode_init(p, APS_PFM);
 662         if (ret < 0)
 663                 return ret;
 664
 665         /* Increase VGEN3 from 2.5 to 2.8V */
 666         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 667         reg &= ~LDO_VOL_MASK;
 668         reg |= LDOB_2_80V;
 669         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
 670
 671         /* Increase VGEN5 from 2.8 to 3V */
 672         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 673         reg &= ~LDO_VOL_MASK;
 674         reg |= LDOB_3_00V;
 675         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 676
 677         return 0;
 678 }
 679
 680 #ifdef CONFIG_MXC_SPI
 681 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 682 {
 683         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 684 }
 685 #endif
 686
 687 #ifdef CONFIG_CMD_BMODE
 688 static const struct boot_mode board_boot_modes[] = {
 689         /* 4 bit bus width */
 690         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 691         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 692         /* 8 bit bus width */
 693         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 694         {NULL,   0},
 695 };
 696 #endif
 697
 698 int board_late_init(void)
 699 {
 700 #ifdef CONFIG_CMD_BMODE
 701         add_board_boot_modes(board_boot_modes);
 702 #endif
 703
 704 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 705         env_set("board_name", "SABRESD");
 706
 707         if (is_mx6dqp())
 708                 env_set("board_rev", "MX6QP");
 709         else if (is_mx6dq())
 710                 env_set("board_rev", "MX6Q");
 711         else if (is_mx6sdl())
 712                 env_set("board_rev", "MX6DL");
 713 #endif
 714
 715         return 0;
 716 }
 717
 718 int checkboard(void)
 719 {
 720         puts("Board: MX6-SabreSD\n");
 721         return 0;
 722 }
 723
 724 #ifdef CONFIG_SPL_BUILD
 725 #include <asm/arch/mx6-ddr.h>
 726 #include <spl.h>
 727 #include <linux/libfdt.h>
 728
 729 #ifdef CONFIG_SPL_OS_BOOT
 730 int spl_start_uboot(void)
 731 {
 732         gpio_direction_input(KEY_VOL_UP);
 733
 734         /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
 735         return gpio_get_value(KEY_VOL_UP);
 736 }
 737 #endif
 738
 739 static void ccgr_init(void)
 740 {
 741         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 742
 743         writel(0x00C03F3F, &ccm->CCGR0);
 744         writel(0x0030FC03, &ccm->CCGR1);
 745         writel(0x0FFFC000, &ccm->CCGR2);
 746         writel(0x3FF00000, &ccm->CCGR3);
 747         writel(0x00FFF300, &ccm->CCGR4);
 748         writel(0x0F0000C3, &ccm->CCGR5);
 749         writel(0x000003FF, &ccm->CCGR6);
 750 }
 751
 752 static int mx6q_dcd_table[] = {
 753         0x020e0798, 0x000C0000,
 754         0x020e0758, 0x00000000,
 755         0x020e0588, 0x00000030,
 756         0x020e0594, 0x00000030,
 757         0x020e056c, 0x00000030,
 758         0x020e0578, 0x00000030,
 759         0x020e074c, 0x00000030,
 760         0x020e057c, 0x00000030,
 761         0x020e058c, 0x00000000,
 762         0x020e059c, 0x00000030,
 763         0x020e05a0, 0x00000030,
 764         0x020e078c, 0x00000030,
 765         0x020e0750, 0x00020000,
 766         0x020e05a8, 0x00000030,
 767         0x020e05b0, 0x00000030,
 768         0x020e0524, 0x00000030,
 769         0x020e051c, 0x00000030,
 770         0x020e0518, 0x00000030,
 771         0x020e050c, 0x00000030,
 772         0x020e05b8, 0x00000030,
 773         0x020e05c0, 0x00000030,
 774         0x020e0774, 0x00020000,
 775         0x020e0784, 0x00000030,
 776         0x020e0788, 0x00000030,
 777         0x020e0794, 0x00000030,
 778         0x020e079c, 0x00000030,
 779         0x020e07a0, 0x00000030,
 780         0x020e07a4, 0x00000030,
 781         0x020e07a8, 0x00000030,
 782         0x020e0748, 0x00000030,
 783         0x020e05ac, 0x00000030,
 784         0x020e05b4, 0x00000030,
 785         0x020e0528, 0x00000030,
 786         0x020e0520, 0x00000030,
 787         0x020e0514, 0x00000030,
 788         0x020e0510, 0x00000030,
 789         0x020e05bc, 0x00000030,
 790         0x020e05c4, 0x00000030,
 791         0x021b0800, 0xa1390003,
 792         0x021b080c, 0x001F001F,
 793         0x021b0810, 0x001F001F,
 794         0x021b480c, 0x001F001F,
 795         0x021b4810, 0x001F001F,
 796         0x021b083c, 0x43270338,
 797         0x021b0840, 0x03200314,
 798         0x021b483c, 0x431A032F,
 799         0x021b4840, 0x03200263,
 800         0x021b0848, 0x4B434748,
 801         0x021b4848, 0x4445404C,
 802         0x021b0850, 0x38444542,
 803         0x021b4850, 0x4935493A,
 804         0x021b081c, 0x33333333,
 805         0x021b0820, 0x33333333,
 806         0x021b0824, 0x33333333,
 807         0x021b0828, 0x33333333,
 808         0x021b481c, 0x33333333,
 809         0x021b4820, 0x33333333,
 810         0x021b4824, 0x33333333,
 811         0x021b4828, 0x33333333,
 812         0x021b08b8, 0x00000800,
 813         0x021b48b8, 0x00000800,
 814         0x021b0004, 0x00020036,
 815         0x021b0008, 0x09444040,
 816         0x021b000c, 0x555A7975,
 817         0x021b0010, 0xFF538F64,
 818         0x021b0014, 0x01FF00DB,
 819         0x021b0018, 0x00001740,
 820         0x021b001c, 0x00008000,
 821         0x021b002c, 0x000026d2,
 822         0x021b0030, 0x005A1023,
 823         0x021b0040, 0x00000027,
 824         0x021b0000, 0x831A0000,
 825         0x021b001c, 0x04088032,
 826         0x021b001c, 0x00008033,
 827         0x021b001c, 0x00048031,
 828         0x021b001c, 0x09408030,
 829         0x021b001c, 0x04008040,
 830         0x021b0020, 0x00005800,
 831         0x021b0818, 0x00011117,
 832         0x021b4818, 0x00011117,
 833         0x021b0004, 0x00025576,
 834         0x021b0404, 0x00011006,
 835         0x021b001c, 0x00000000,
 836 };
 837
 838 static int mx6qp_dcd_table[] = {
 839         0x020e0798, 0x000c0000,
 840         0x020e0758, 0x00000000,
 841         0x020e0588, 0x00000030,
 842         0x020e0594, 0x00000030,
 843         0x020e056c, 0x00000030,
 844         0x020e0578, 0x00000030,
 845         0x020e074c, 0x00000030,
 846         0x020e057c, 0x00000030,
 847         0x020e058c, 0x00000000,
 848         0x020e059c, 0x00000030,
 849         0x020e05a0, 0x00000030,
 850         0x020e078c, 0x00000030,
 851         0x020e0750, 0x00020000,
 852         0x020e05a8, 0x00000030,
 853         0x020e05b0, 0x00000030,
 854         0x020e0524, 0x00000030,
 855         0x020e051c, 0x00000030,
 856         0x020e0518, 0x00000030,
 857         0x020e050c, 0x00000030,
 858         0x020e05b8, 0x00000030,
 859         0x020e05c0, 0x00000030,
 860         0x020e0774, 0x00020000,
 861         0x020e0784, 0x00000030,
 862         0x020e0788, 0x00000030,
 863         0x020e0794, 0x00000030,
 864         0x020e079c, 0x00000030,
 865         0x020e07a0, 0x00000030,
 866         0x020e07a4, 0x00000030,
 867         0x020e07a8, 0x00000030,
 868         0x020e0748, 0x00000030,
 869         0x020e05ac, 0x00000030,
 870         0x020e05b4, 0x00000030,
 871         0x020e0528, 0x00000030,
 872         0x020e0520, 0x00000030,
 873         0x020e0514, 0x00000030,
 874         0x020e0510, 0x00000030,
 875         0x020e05bc, 0x00000030,
 876         0x020e05c4, 0x00000030,
 877         0x021b0800, 0xa1390003,
 878         0x021b080c, 0x001b001e,
 879         0x021b0810, 0x002e0029,
 880         0x021b480c, 0x001b002a,
 881         0x021b4810, 0x0019002c,
 882         0x021b083c, 0x43240334,
 883         0x021b0840, 0x0324031a,
 884         0x021b483c, 0x43340344,
 885         0x021b4840, 0x03280276,
 886         0x021b0848, 0x44383A3E,
 887         0x021b4848, 0x3C3C3846,
 888         0x021b0850, 0x2e303230,
 889         0x021b4850, 0x38283E34,
 890         0x021b081c, 0x33333333,
 891         0x021b0820, 0x33333333,
 892         0x021b0824, 0x33333333,
 893         0x021b0828, 0x33333333,
 894         0x021b481c, 0x33333333,
 895         0x021b4820, 0x33333333,
 896         0x021b4824, 0x33333333,
 897         0x021b4828, 0x33333333,
 898         0x021b08c0, 0x24912249,
 899         0x021b48c0, 0x24914289,
 900         0x021b08b8, 0x00000800,
 901         0x021b48b8, 0x00000800,
 902         0x021b0004, 0x00020036,
 903         0x021b0008, 0x24444040,
 904         0x021b000c, 0x555A7955,
 905         0x021b0010, 0xFF320F64,
 906         0x021b0014, 0x01ff00db,
 907         0x021b0018, 0x00001740,
 908         0x021b001c, 0x00008000,
 909         0x021b002c, 0x000026d2,
 910         0x021b0030, 0x005A1023,
 911         0x021b0040, 0x00000027,
 912         0x021b0400, 0x14420000,
 913         0x021b0000, 0x831A0000,
 914         0x021b0890, 0x00400C58,
 915         0x00bb0008, 0x00000000,
 916         0x00bb000c, 0x2891E41A,
 917         0x00bb0038, 0x00000564,
 918         0x00bb0014, 0x00000040,
 919         0x00bb0028, 0x00000020,
 920         0x00bb002c, 0x00000020,
 921         0x021b001c, 0x04088032,
 922         0x021b001c, 0x00008033,
 923         0x021b001c, 0x00048031,
 924         0x021b001c, 0x09408030,
 925         0x021b001c, 0x04008040,
 926         0x021b0020, 0x00005800,
 927         0x021b0818, 0x00011117,
 928         0x021b4818, 0x00011117,
 929         0x021b0004, 0x00025576,
 930         0x021b0404, 0x00011006,
 931         0x021b001c, 0x00000000,
 932 };
 933
 934 static int mx6dl_dcd_table[] = {
 935         0x020e0774, 0x000C0000,
 936         0x020e0754, 0x00000000,
 937         0x020e04ac, 0x00000030,
 938         0x020e04b0, 0x00000030,
 939         0x020e0464, 0x00000030,
 940         0x020e0490, 0x00000030,
 941         0x020e074c, 0x00000030,
 942         0x020e0494, 0x00000030,
 943         0x020e04a0, 0x00000000,
 944         0x020e04b4, 0x00000030,
 945         0x020e04b8, 0x00000030,
 946         0x020e076c, 0x00000030,
 947         0x020e0750, 0x00020000,
 948         0x020e04bc, 0x00000030,
 949         0x020e04c0, 0x00000030,
 950         0x020e04c4, 0x00000030,
 951         0x020e04c8, 0x00000030,
 952         0x020e04cc, 0x00000030,
 953         0x020e04d0, 0x00000030,
 954         0x020e04d4, 0x00000030,
 955         0x020e04d8, 0x00000030,
 956         0x020e0760, 0x00020000,
 957         0x020e0764, 0x00000030,
 958         0x020e0770, 0x00000030,
 959         0x020e0778, 0x00000030,
 960         0x020e077c, 0x00000030,
 961         0x020e0780, 0x00000030,
 962         0x020e0784, 0x00000030,
 963         0x020e078c, 0x00000030,
 964         0x020e0748, 0x00000030,
 965         0x020e0470, 0x00000030,
 966         0x020e0474, 0x00000030,
 967         0x020e0478, 0x00000030,
 968         0x020e047c, 0x00000030,
 969         0x020e0480, 0x00000030,
 970         0x020e0484, 0x00000030,
 971         0x020e0488, 0x00000030,
 972         0x020e048c, 0x00000030,
 973         0x021b0800, 0xa1390003,
 974         0x021b080c, 0x001F001F,
 975         0x021b0810, 0x001F001F,
 976         0x021b480c, 0x001F001F,
 977         0x021b4810, 0x001F001F,
 978         0x021b083c, 0x4220021F,
 979         0x021b0840, 0x0207017E,
 980         0x021b483c, 0x4201020C,
 981         0x021b4840, 0x01660172,
 982         0x021b0848, 0x4A4D4E4D,
 983         0x021b4848, 0x4A4F5049,
 984         0x021b0850, 0x3F3C3D31,
 985         0x021b4850, 0x3238372B,
 986         0x021b081c, 0x33333333,
 987         0x021b0820, 0x33333333,
 988         0x021b0824, 0x33333333,
 989         0x021b0828, 0x33333333,
 990         0x021b481c, 0x33333333,
 991         0x021b4820, 0x33333333,
 992         0x021b4824, 0x33333333,
 993         0x021b4828, 0x33333333,
 994         0x021b08b8, 0x00000800,
 995         0x021b48b8, 0x00000800,
 996         0x021b0004, 0x0002002D,
 997         0x021b0008, 0x00333030,
 998         0x021b000c, 0x3F435313,
 999         0x021b0010, 0xB66E8B63,
1000         0x021b0014, 0x01FF00DB,
1001         0x021b0018, 0x00001740,
1002         0x021b001c, 0x00008000,
1003         0x021b002c, 0x000026d2,
1004         0x021b0030, 0x00431023,
1005         0x021b0040, 0x00000027,
1006         0x021b0000, 0x831A0000,
1007         0x021b001c, 0x04008032,
1008         0x021b001c, 0x00008033,
1009         0x021b001c, 0x00048031,
1010         0x021b001c, 0x05208030,
1011         0x021b001c, 0x04008040,
1012         0x021b0020, 0x00005800,
1013         0x021b0818, 0x00011117,
1014         0x021b4818, 0x00011117,
1015         0x021b0004, 0x0002556D,
1016         0x021b0404, 0x00011006,
1017         0x021b001c, 0x00000000,
1018 };
1019
1020 static void ddr_init(int *table, int size)
1021 {
1022         int i;
1023
1024         for (i = 0; i < size / 2 ; i++)
1025                 writel(table[2 * i + 1], table[2 * i]);
1026 }
1027
1028 static void spl_dram_init(void)
1029 {
1030         if (is_mx6dq())
1031                 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
1032         else if (is_mx6dqp())
1033                 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
1034         else if (is_mx6sdl())
1035                 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1036 }
1037
1038 void board_init_f(ulong dummy)
1039 {
1040         /* DDR initialization */
1041         spl_dram_init();
1042
1043         /* setup AIPS and disable watchdog */
1044         arch_cpu_init();
1045
1046         ccgr_init();
1047         gpr_init();
1048
1049         /* iomux and setup of i2c */
1050         board_early_init_f();
1051
1052         /* setup GP timer */
1053         timer_init();
1054
1055         /* UART clocks enabled and gd valid - init serial console */
1056         preloader_console_init();
1057
1058         /* Clear the BSS. */
1059         memset(__bss_start, 0, __bss_end - __bss_start);
1060
1061         /* load/boot image from boot device */
1062         board_init_r(NULL, 0);
1063 }
1064 #endif