board/freescale/mx6sabresd/mx6sabresd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <asm/mach-imx/spi.h>
  13 #include <env.h>
  14 #include <linux/errno.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/mxc_i2c.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <i2c.h>
  29 #include <input.h>
  30 #include <power/pmic.h>
  31 #include <power/pfuze100_pmic.h>
  32 #include "../common/pfuze.h"
  33 #include <usb.h>
  34 #include <usb/ehci-ci.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  43         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  50                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  51
  52 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  54         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55
  56 #define I2C_PMIC        1
  57
  58 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  59
  60 #define DISP0_PWR_EN    IMX_GPIO_NR(1, 21)
  61
  62 #define KEY_VOL_UP      IMX_GPIO_NR(1, 4)
  63
  64 int dram_init(void)
  65 {
  66         gd->ram_size = imx_ddr_size();
  67         return 0;
  68 }
  69
  70 static iomux_v3_cfg_t const uart1_pads[] = {
  71         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  72         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  73 };
  74
  75 static iomux_v3_cfg_t const enet_pads[] = {
  76         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK        | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91         /* AR8031 PHY Reset */
  92         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93 };
  94
  95 static void setup_iomux_enet(void)
  96 {
  97         SETUP_IOMUX_PADS(enet_pads);
  98 }
  99
 100 static iomux_v3_cfg_t const usdhc2_pads[] = {
 101         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 102         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 103         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 104         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 105         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 106         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 107         IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 108         IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 109         IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 110         IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 111         IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02     | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 112 };
 113
 114 static iomux_v3_cfg_t const usdhc3_pads[] = {
 115         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 116         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 117         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 118         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 119         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 120         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 121         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 122         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 123         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 126 };
 127
 128 static iomux_v3_cfg_t const usdhc4_pads[] = {
 129         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 130         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 131         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 132         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139 };
 140
 141 static iomux_v3_cfg_t const ecspi1_pads[] = {
 142         IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 143         IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 144         IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 145         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 146 };
 147
 148 static iomux_v3_cfg_t const rgb_pads[] = {
 149         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
 150         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 151         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 152         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 153         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 154         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 155         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 156         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 157         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 158         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 159         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 160         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 161         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 162         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 163         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 164         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 165         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 166         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 167         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 168         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 169         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 170         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 171         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 172         IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 173         IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 174         IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 175         IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 176         IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 177         IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 178 };
 179
 180 static iomux_v3_cfg_t const bl_pads[] = {
 181         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 182 };
 183
 184 static void enable_backlight(void)
 185 {
 186         SETUP_IOMUX_PADS(bl_pads);
 187         gpio_request(DISP0_PWR_EN, "Display Power Enable");
 188         gpio_direction_output(DISP0_PWR_EN, 1);
 189 }
 190
 191 static void enable_rgb(struct display_info_t const *dev)
 192 {
 193         SETUP_IOMUX_PADS(rgb_pads);
 194         enable_backlight();
 195 }
 196
 197 static void enable_lvds(struct display_info_t const *dev)
 198 {
 199         enable_backlight();
 200 }
 201
 202 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
 203         .scl = {
 204                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 205                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 206                 .gp = IMX_GPIO_NR(4, 12)
 207         },
 208         .sda = {
 209                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 210                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 211                 .gp = IMX_GPIO_NR(4, 13)
 212         }
 213 };
 214
 215 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 216         .scl = {
 217                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 218                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 219                 .gp = IMX_GPIO_NR(4, 12)
 220         },
 221         .sda = {
 222                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 223                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 224                 .gp = IMX_GPIO_NR(4, 13)
 225         }
 226 };
 227
 228 static void setup_spi(void)
 229 {
 230         SETUP_IOMUX_PADS(ecspi1_pads);
 231 }
 232
 233 iomux_v3_cfg_t const pcie_pads[] = {
 234         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),        /* POWER */
 235         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),        /* RESET */
 236 };
 237
 238 static void setup_pcie(void)
 239 {
 240         SETUP_IOMUX_PADS(pcie_pads);
 241 }
 242
 243 iomux_v3_cfg_t const di0_pads[] = {
 244         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),        /* DISP0_CLK */
 245         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),               /* DISP0_HSYNC */
 246         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),               /* DISP0_VSYNC */
 247 };
 248
 249 static void setup_iomux_uart(void)
 250 {
 251         SETUP_IOMUX_PADS(uart1_pads);
 252 }
 253
 254 #ifdef CONFIG_FSL_ESDHC_IMX
 255 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 256         {USDHC2_BASE_ADDR},
 257         {USDHC3_BASE_ADDR},
 258         {USDHC4_BASE_ADDR},
 259 };
 260
 261 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 262 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 263
 264 int board_mmc_get_env_dev(int devno)
 265 {
 266         return devno - 1;
 267 }
 268
 269 int board_mmc_getcd(struct mmc *mmc)
 270 {
 271         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 272         int ret = 0;
 273
 274         switch (cfg->esdhc_base) {
 275         case USDHC2_BASE_ADDR:
 276                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 277                 break;
 278         case USDHC3_BASE_ADDR:
 279                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 280                 break;
 281         case USDHC4_BASE_ADDR:
 282                 ret = 1; /* eMMC/uSDHC4 is always present */
 283                 break;
 284         }
 285
 286         return ret;
 287 }
 288
 289 int board_mmc_init(bd_t *bis)
 290 {
 291         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 292         unsigned reg = readl(&psrc->sbmr1) >> 11;
 293         /*
 294          * Upon reading BOOT_CFG register the following map is done:
 295          * Bit 11 and 12 of BOOT_CFG register can determine the current
 296          * mmc port
 297          * 0x1                  SD1
 298          * 0x2                  SD2
 299          * 0x3                  SD4
 300          */
 301
 302         switch (reg & 0x3) {
 303         case 0x1:
 304                 SETUP_IOMUX_PADS(usdhc2_pads);
 305                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 306                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 307                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 308                 break;
 309         case 0x2:
 310                 SETUP_IOMUX_PADS(usdhc3_pads);
 311                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 312                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 313                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 314                 break;
 315         case 0x3:
 316                 SETUP_IOMUX_PADS(usdhc4_pads);
 317                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 318                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 319                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 320                 break;
 321         }
 322
 323         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 324 }
 325 #endif
 326
 327 static int ar8031_phy_fixup(struct phy_device *phydev)
 328 {
 329         unsigned short val;
 330
 331         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 332         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 333         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 334         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 335
 336         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 337         val &= 0xffe3;
 338         val |= 0x18;
 339         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 340
 341         /* introduce tx clock delay */
 342         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 343         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 344         val |= 0x0100;
 345         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 346
 347         return 0;
 348 }
 349
 350 int board_phy_config(struct phy_device *phydev)
 351 {
 352         ar8031_phy_fixup(phydev);
 353
 354         if (phydev->drv->config)
 355                 phydev->drv->config(phydev);
 356
 357         return 0;
 358 }
 359
 360 #if defined(CONFIG_VIDEO_IPUV3)
 361 static void disable_lvds(struct display_info_t const *dev)
 362 {
 363         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 364
 365         int reg = readl(&iomux->gpr[2]);
 366
 367         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 368                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 369
 370         writel(reg, &iomux->gpr[2]);
 371 }
 372
 373 static void do_enable_hdmi(struct display_info_t const *dev)
 374 {
 375         disable_lvds(dev);
 376         imx_enable_hdmi_phy();
 377 }
 378
 379 struct display_info_t const displays[] = {{
 380         .bus    = -1,
 381         .addr   = 0,
 382         .pixfmt = IPU_PIX_FMT_RGB666,
 383         .detect = NULL,
 384         .enable = enable_lvds,
 385         .mode   = {
 386                 .name           = "Hannstar-XGA",
 387                 .refresh        = 60,
 388                 .xres           = 1024,
 389                 .yres           = 768,
 390                 .pixclock       = 15384,
 391                 .left_margin    = 160,
 392                 .right_margin   = 24,
 393                 .upper_margin   = 29,
 394                 .lower_margin   = 3,
 395                 .hsync_len      = 136,
 396                 .vsync_len      = 6,
 397                 .sync           = FB_SYNC_EXT,
 398                 .vmode          = FB_VMODE_NONINTERLACED
 399 } }, {
 400         .bus    = -1,
 401         .addr   = 0,
 402         .pixfmt = IPU_PIX_FMT_RGB24,
 403         .detect = detect_hdmi,
 404         .enable = do_enable_hdmi,
 405         .mode   = {
 406                 .name           = "HDMI",
 407                 .refresh        = 60,
 408                 .xres           = 1024,
 409                 .yres           = 768,
 410                 .pixclock       = 15384,
 411                 .left_margin    = 160,
 412                 .right_margin   = 24,
 413                 .upper_margin   = 29,
 414                 .lower_margin   = 3,
 415                 .hsync_len      = 136,
 416                 .vsync_len      = 6,
 417                 .sync           = FB_SYNC_EXT,
 418                 .vmode          = FB_VMODE_NONINTERLACED
 419 } }, {
 420         .bus    = 0,
 421         .addr   = 0,
 422         .pixfmt = IPU_PIX_FMT_RGB24,
 423         .detect = NULL,
 424         .enable = enable_rgb,
 425         .mode   = {
 426                 .name           = "SEIKO-WVGA",
 427                 .refresh        = 60,
 428                 .xres           = 800,
 429                 .yres           = 480,
 430                 .pixclock       = 29850,
 431                 .left_margin    = 89,
 432                 .right_margin   = 164,
 433                 .upper_margin   = 23,
 434                 .lower_margin   = 10,
 435                 .hsync_len      = 10,
 436                 .vsync_len      = 10,
 437                 .sync           = 0,
 438                 .vmode          = FB_VMODE_NONINTERLACED
 439 } } };
 440 size_t display_count = ARRAY_SIZE(displays);
 441
 442 static void setup_display(void)
 443 {
 444         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 445         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 446         int reg;
 447
 448         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 449         SETUP_IOMUX_PADS(di0_pads);
 450
 451         enable_ipu_clock();
 452         imx_setup_hdmi();
 453
 454         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 455         reg = readl(&mxc_ccm->CCGR3);
 456         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 457         writel(reg, &mxc_ccm->CCGR3);
 458
 459         /* set LDB0, LDB1 clk select to 011/011 */
 460         reg = readl(&mxc_ccm->cs2cdr);
 461         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 462                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 463         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 464               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 465         writel(reg, &mxc_ccm->cs2cdr);
 466
 467         reg = readl(&mxc_ccm->cscmr2);
 468         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 469         writel(reg, &mxc_ccm->cscmr2);
 470
 471         reg = readl(&mxc_ccm->chsccdr);
 472         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 473                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 474         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 475                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 476         writel(reg, &mxc_ccm->chsccdr);
 477
 478         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 479              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 480              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 481              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 482              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 483              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 484              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 485              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 486              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 487         writel(reg, &iomux->gpr[2]);
 488
 489         reg = readl(&iomux->gpr[3]);
 490         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 491                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 492             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 493                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 494         writel(reg, &iomux->gpr[3]);
 495 }
 496 #endif /* CONFIG_VIDEO_IPUV3 */
 497
 498 /*
 499  * Do not overwrite the console
 500  * Use always serial for U-Boot console
 501  */
 502 int overwrite_console(void)
 503 {
 504         return 1;
 505 }
 506
 507 int board_eth_init(bd_t *bis)
 508 {
 509         setup_iomux_enet();
 510         setup_pcie();
 511
 512         return cpu_eth_init(bis);
 513 }
 514
 515 #ifdef CONFIG_USB_EHCI_MX6
 516 static void setup_usb(void)
 517 {
 518         /*
 519          * set daisy chain for otg_pin_id on 6q.
 520          * for 6dl, this bit is reserved
 521          */
 522         imx_iomux_set_gpr_register(1, 13, 1, 0);
 523 }
 524 #endif
 525
 526 int board_early_init_f(void)
 527 {
 528         setup_iomux_uart();
 529
 530         return 0;
 531 }
 532
 533 int board_init(void)
 534 {
 535         /* address of boot parameters */
 536         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 537
 538 #ifdef CONFIG_MXC_SPI
 539         setup_spi();
 540 #endif
 541         if (is_mx6dq() || is_mx6dqp())
 542                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 543         else
 544                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 545 #if defined(CONFIG_VIDEO_IPUV3)
 546         setup_display();
 547 #endif
 548 #ifdef CONFIG_USB_EHCI_MX6
 549         setup_usb();
 550 #endif
 551
 552         return 0;
 553 }
 554
 555 int power_init_board(void)
 556 {
 557         struct pmic *p;
 558         unsigned int reg;
 559         int ret;
 560
 561         p = pfuze_common_init(I2C_PMIC);
 562         if (!p)
 563                 return -ENODEV;
 564
 565         ret = pfuze_mode_init(p, APS_PFM);
 566         if (ret < 0)
 567                 return ret;
 568
 569         /* Increase VGEN3 from 2.5 to 2.8V */
 570         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 571         reg &= ~LDO_VOL_MASK;
 572         reg |= LDOB_2_80V;
 573         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
 574
 575         /* Increase VGEN5 from 2.8 to 3V */
 576         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 577         reg &= ~LDO_VOL_MASK;
 578         reg |= LDOB_3_00V;
 579         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 580
 581         return 0;
 582 }
 583
 584 #ifdef CONFIG_MXC_SPI
 585 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 586 {
 587         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 588 }
 589 #endif
 590
 591 #ifdef CONFIG_CMD_BMODE
 592 static const struct boot_mode board_boot_modes[] = {
 593         /* 4 bit bus width */
 594         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 595         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 596         /* 8 bit bus width */
 597         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 598         {NULL,   0},
 599 };
 600 #endif
 601
 602 int board_late_init(void)
 603 {
 604 #ifdef CONFIG_CMD_BMODE
 605         add_board_boot_modes(board_boot_modes);
 606 #endif
 607
 608 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 609         env_set("board_name", "SABRESD");
 610
 611         if (is_mx6dqp())
 612                 env_set("board_rev", "MX6QP");
 613         else if (is_mx6dq())
 614                 env_set("board_rev", "MX6Q");
 615         else if (is_mx6sdl())
 616                 env_set("board_rev", "MX6DL");
 617 #endif
 618
 619         return 0;
 620 }
 621
 622 int checkboard(void)
 623 {
 624         puts("Board: MX6-SabreSD\n");
 625         return 0;
 626 }
 627
 628 #ifdef CONFIG_SPL_BUILD
 629 #include <asm/arch/mx6-ddr.h>
 630 #include <spl.h>
 631 #include <linux/libfdt.h>
 632
 633 #ifdef CONFIG_SPL_OS_BOOT
 634 int spl_start_uboot(void)
 635 {
 636         gpio_request(KEY_VOL_UP, "KEY Volume UP");
 637         gpio_direction_input(KEY_VOL_UP);
 638
 639         /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
 640         return gpio_get_value(KEY_VOL_UP);
 641 }
 642 #endif
 643
 644 static void ccgr_init(void)
 645 {
 646         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 647
 648         writel(0x00C03F3F, &ccm->CCGR0);
 649         writel(0x0030FC03, &ccm->CCGR1);
 650         writel(0x0FFFC000, &ccm->CCGR2);
 651         writel(0x3FF00000, &ccm->CCGR3);
 652         writel(0x00FFF300, &ccm->CCGR4);
 653         writel(0x0F0000C3, &ccm->CCGR5);
 654         writel(0x000003FF, &ccm->CCGR6);
 655 }
 656
 657 static int mx6q_dcd_table[] = {
 658         0x020e0798, 0x000C0000,
 659         0x020e0758, 0x00000000,
 660         0x020e0588, 0x00000030,
 661         0x020e0594, 0x00000030,
 662         0x020e056c, 0x00000030,
 663         0x020e0578, 0x00000030,
 664         0x020e074c, 0x00000030,
 665         0x020e057c, 0x00000030,
 666         0x020e058c, 0x00000000,
 667         0x020e059c, 0x00000030,
 668         0x020e05a0, 0x00000030,
 669         0x020e078c, 0x00000030,
 670         0x020e0750, 0x00020000,
 671         0x020e05a8, 0x00000030,
 672         0x020e05b0, 0x00000030,
 673         0x020e0524, 0x00000030,
 674         0x020e051c, 0x00000030,
 675         0x020e0518, 0x00000030,
 676         0x020e050c, 0x00000030,
 677         0x020e05b8, 0x00000030,
 678         0x020e05c0, 0x00000030,
 679         0x020e0774, 0x00020000,
 680         0x020e0784, 0x00000030,
 681         0x020e0788, 0x00000030,
 682         0x020e0794, 0x00000030,
 683         0x020e079c, 0x00000030,
 684         0x020e07a0, 0x00000030,
 685         0x020e07a4, 0x00000030,
 686         0x020e07a8, 0x00000030,
 687         0x020e0748, 0x00000030,
 688         0x020e05ac, 0x00000030,
 689         0x020e05b4, 0x00000030,
 690         0x020e0528, 0x00000030,
 691         0x020e0520, 0x00000030,
 692         0x020e0514, 0x00000030,
 693         0x020e0510, 0x00000030,
 694         0x020e05bc, 0x00000030,
 695         0x020e05c4, 0x00000030,
 696         0x021b0800, 0xa1390003,
 697         0x021b080c, 0x001F001F,
 698         0x021b0810, 0x001F001F,
 699         0x021b480c, 0x001F001F,
 700         0x021b4810, 0x001F001F,
 701         0x021b083c, 0x43270338,
 702         0x021b0840, 0x03200314,
 703         0x021b483c, 0x431A032F,
 704         0x021b4840, 0x03200263,
 705         0x021b0848, 0x4B434748,
 706         0x021b4848, 0x4445404C,
 707         0x021b0850, 0x38444542,
 708         0x021b4850, 0x4935493A,
 709         0x021b081c, 0x33333333,
 710         0x021b0820, 0x33333333,
 711         0x021b0824, 0x33333333,
 712         0x021b0828, 0x33333333,
 713         0x021b481c, 0x33333333,
 714         0x021b4820, 0x33333333,
 715         0x021b4824, 0x33333333,
 716         0x021b4828, 0x33333333,
 717         0x021b08b8, 0x00000800,
 718         0x021b48b8, 0x00000800,
 719         0x021b0004, 0x00020036,
 720         0x021b0008, 0x09444040,
 721         0x021b000c, 0x555A7975,
 722         0x021b0010, 0xFF538F64,
 723         0x021b0014, 0x01FF00DB,
 724         0x021b0018, 0x00001740,
 725         0x021b001c, 0x00008000,
 726         0x021b002c, 0x000026d2,
 727         0x021b0030, 0x005A1023,
 728         0x021b0040, 0x00000027,
 729         0x021b0000, 0x831A0000,
 730         0x021b001c, 0x04088032,
 731         0x021b001c, 0x00008033,
 732         0x021b001c, 0x00048031,
 733         0x021b001c, 0x09408030,
 734         0x021b001c, 0x04008040,
 735         0x021b0020, 0x00005800,
 736         0x021b0818, 0x00011117,
 737         0x021b4818, 0x00011117,
 738         0x021b0004, 0x00025576,
 739         0x021b0404, 0x00011006,
 740         0x021b001c, 0x00000000,
 741 };
 742
 743 static int mx6qp_dcd_table[] = {
 744         0x020e0798, 0x000c0000,
 745         0x020e0758, 0x00000000,
 746         0x020e0588, 0x00000030,
 747         0x020e0594, 0x00000030,
 748         0x020e056c, 0x00000030,
 749         0x020e0578, 0x00000030,
 750         0x020e074c, 0x00000030,
 751         0x020e057c, 0x00000030,
 752         0x020e058c, 0x00000000,
 753         0x020e059c, 0x00000030,
 754         0x020e05a0, 0x00000030,
 755         0x020e078c, 0x00000030,
 756         0x020e0750, 0x00020000,
 757         0x020e05a8, 0x00000030,
 758         0x020e05b0, 0x00000030,
 759         0x020e0524, 0x00000030,
 760         0x020e051c, 0x00000030,
 761         0x020e0518, 0x00000030,
 762         0x020e050c, 0x00000030,
 763         0x020e05b8, 0x00000030,
 764         0x020e05c0, 0x00000030,
 765         0x020e0774, 0x00020000,
 766         0x020e0784, 0x00000030,
 767         0x020e0788, 0x00000030,
 768         0x020e0794, 0x00000030,
 769         0x020e079c, 0x00000030,
 770         0x020e07a0, 0x00000030,
 771         0x020e07a4, 0x00000030,
 772         0x020e07a8, 0x00000030,
 773         0x020e0748, 0x00000030,
 774         0x020e05ac, 0x00000030,
 775         0x020e05b4, 0x00000030,
 776         0x020e0528, 0x00000030,
 777         0x020e0520, 0x00000030,
 778         0x020e0514, 0x00000030,
 779         0x020e0510, 0x00000030,
 780         0x020e05bc, 0x00000030,
 781         0x020e05c4, 0x00000030,
 782         0x021b0800, 0xa1390003,
 783         0x021b080c, 0x001b001e,
 784         0x021b0810, 0x002e0029,
 785         0x021b480c, 0x001b002a,
 786         0x021b4810, 0x0019002c,
 787         0x021b083c, 0x43240334,
 788         0x021b0840, 0x0324031a,
 789         0x021b483c, 0x43340344,
 790         0x021b4840, 0x03280276,
 791         0x021b0848, 0x44383A3E,
 792         0x021b4848, 0x3C3C3846,
 793         0x021b0850, 0x2e303230,
 794         0x021b4850, 0x38283E34,
 795         0x021b081c, 0x33333333,
 796         0x021b0820, 0x33333333,
 797         0x021b0824, 0x33333333,
 798         0x021b0828, 0x33333333,
 799         0x021b481c, 0x33333333,
 800         0x021b4820, 0x33333333,
 801         0x021b4824, 0x33333333,
 802         0x021b4828, 0x33333333,
 803         0x021b08c0, 0x24912249,
 804         0x021b48c0, 0x24914289,
 805         0x021b08b8, 0x00000800,
 806         0x021b48b8, 0x00000800,
 807         0x021b0004, 0x00020036,
 808         0x021b0008, 0x24444040,
 809         0x021b000c, 0x555A7955,
 810         0x021b0010, 0xFF320F64,
 811         0x021b0014, 0x01ff00db,
 812         0x021b0018, 0x00001740,
 813         0x021b001c, 0x00008000,
 814         0x021b002c, 0x000026d2,
 815         0x021b0030, 0x005A1023,
 816         0x021b0040, 0x00000027,
 817         0x021b0400, 0x14420000,
 818         0x021b0000, 0x831A0000,
 819         0x021b0890, 0x00400C58,
 820         0x00bb0008, 0x00000000,
 821         0x00bb000c, 0x2891E41A,
 822         0x00bb0038, 0x00000564,
 823         0x00bb0014, 0x00000040,
 824         0x00bb0028, 0x00000020,
 825         0x00bb002c, 0x00000020,
 826         0x021b001c, 0x04088032,
 827         0x021b001c, 0x00008033,
 828         0x021b001c, 0x00048031,
 829         0x021b001c, 0x09408030,
 830         0x021b001c, 0x04008040,
 831         0x021b0020, 0x00005800,
 832         0x021b0818, 0x00011117,
 833         0x021b4818, 0x00011117,
 834         0x021b0004, 0x00025576,
 835         0x021b0404, 0x00011006,
 836         0x021b001c, 0x00000000,
 837 };
 838
 839 static int mx6dl_dcd_table[] = {
 840         0x020e0774, 0x000C0000,
 841         0x020e0754, 0x00000000,
 842         0x020e04ac, 0x00000030,
 843         0x020e04b0, 0x00000030,
 844         0x020e0464, 0x00000030,
 845         0x020e0490, 0x00000030,
 846         0x020e074c, 0x00000030,
 847         0x020e0494, 0x00000030,
 848         0x020e04a0, 0x00000000,
 849         0x020e04b4, 0x00000030,
 850         0x020e04b8, 0x00000030,
 851         0x020e076c, 0x00000030,
 852         0x020e0750, 0x00020000,
 853         0x020e04bc, 0x00000030,
 854         0x020e04c0, 0x00000030,
 855         0x020e04c4, 0x00000030,
 856         0x020e04c8, 0x00000030,
 857         0x020e04cc, 0x00000030,
 858         0x020e04d0, 0x00000030,
 859         0x020e04d4, 0x00000030,
 860         0x020e04d8, 0x00000030,
 861         0x020e0760, 0x00020000,
 862         0x020e0764, 0x00000030,
 863         0x020e0770, 0x00000030,
 864         0x020e0778, 0x00000030,
 865         0x020e077c, 0x00000030,
 866         0x020e0780, 0x00000030,
 867         0x020e0784, 0x00000030,
 868         0x020e078c, 0x00000030,
 869         0x020e0748, 0x00000030,
 870         0x020e0470, 0x00000030,
 871         0x020e0474, 0x00000030,
 872         0x020e0478, 0x00000030,
 873         0x020e047c, 0x00000030,
 874         0x020e0480, 0x00000030,
 875         0x020e0484, 0x00000030,
 876         0x020e0488, 0x00000030,
 877         0x020e048c, 0x00000030,
 878         0x021b0800, 0xa1390003,
 879         0x021b080c, 0x001F001F,
 880         0x021b0810, 0x001F001F,
 881         0x021b480c, 0x001F001F,
 882         0x021b4810, 0x001F001F,
 883         0x021b083c, 0x4220021F,
 884         0x021b0840, 0x0207017E,
 885         0x021b483c, 0x4201020C,
 886         0x021b4840, 0x01660172,
 887         0x021b0848, 0x4A4D4E4D,
 888         0x021b4848, 0x4A4F5049,
 889         0x021b0850, 0x3F3C3D31,
 890         0x021b4850, 0x3238372B,
 891         0x021b081c, 0x33333333,
 892         0x021b0820, 0x33333333,
 893         0x021b0824, 0x33333333,
 894         0x021b0828, 0x33333333,
 895         0x021b481c, 0x33333333,
 896         0x021b4820, 0x33333333,
 897         0x021b4824, 0x33333333,
 898         0x021b4828, 0x33333333,
 899         0x021b08b8, 0x00000800,
 900         0x021b48b8, 0x00000800,
 901         0x021b0004, 0x0002002D,
 902         0x021b0008, 0x00333030,
 903         0x021b000c, 0x3F435313,
 904         0x021b0010, 0xB66E8B63,
 905         0x021b0014, 0x01FF00DB,
 906         0x021b0018, 0x00001740,
 907         0x021b001c, 0x00008000,
 908         0x021b002c, 0x000026d2,
 909         0x021b0030, 0x00431023,
 910         0x021b0040, 0x00000027,
 911         0x021b0000, 0x831A0000,
 912         0x021b001c, 0x04008032,
 913         0x021b001c, 0x00008033,
 914         0x021b001c, 0x00048031,
 915         0x021b001c, 0x05208030,
 916         0x021b001c, 0x04008040,
 917         0x021b0020, 0x00005800,
 918         0x021b0818, 0x00011117,
 919         0x021b4818, 0x00011117,
 920         0x021b0004, 0x0002556D,
 921         0x021b0404, 0x00011006,
 922         0x021b001c, 0x00000000,
 923 };
 924
 925 static void ddr_init(int *table, int size)
 926 {
 927         int i;
 928
 929         for (i = 0; i < size / 2 ; i++)
 930                 writel(table[2 * i + 1], table[2 * i]);
 931 }
 932
 933 static void spl_dram_init(void)
 934 {
 935         if (is_mx6dq())
 936                 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
 937         else if (is_mx6dqp())
 938                 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
 939         else if (is_mx6sdl())
 940                 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
 941 }
 942
 943 void board_init_f(ulong dummy)
 944 {
 945         /* DDR initialization */
 946         spl_dram_init();
 947
 948         /* setup AIPS and disable watchdog */
 949         arch_cpu_init();
 950
 951         ccgr_init();
 952         gpr_init();
 953
 954         /* iomux and setup of i2c */
 955         board_early_init_f();
 956
 957         /* setup GP timer */
 958         timer_init();
 959
 960         /* UART clocks enabled and gd valid - init serial console */
 961         preloader_console_init();
 962
 963         /* Clear the BSS. */
 964         memset(__bss_start, 0, __bss_end - __bss_start);
 965
 966         /* load/boot image from boot device */
 967         board_init_r(NULL, 0);
 968 }
 969 #endif
 970
 971 #ifdef CONFIG_SPL_LOAD_FIT
 972 int board_fit_config_name_match(const char *name)
 973 {
 974         if (is_mx6dq()) {
 975                 if (!strcmp(name, "imx6q-sabresd"))
 976                         return 0;
 977         } else if (is_mx6dqp()) {
 978                 if (!strcmp(name, "imx6qp-sabresd"))
 979                         return 0;
 980         } else if (is_mx6dl()) {
 981                 if (!strcmp(name, "imx6dl-sabresd"))
 982                         return 0;
 983         }
 984
 985         return -1;
 986 }
 987 #endif