board/freescale/mx6sabreauto/mx6sabreauto.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <env.h>
  15 #include <linux/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/spi.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <miiphy.h>
  24 #include <netdev.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <i2c.h>
  27 #include <input.h>
  28 #include <asm/arch/mxc_hdmi.h>
  29 #include <asm/mach-imx/video.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <pca953x.h>
  32 #include <power/pmic.h>
  33 #include <power/pfuze100_pmic.h>
  34 #include "../common/pfuze.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  43         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  51         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  52
  53 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  54 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  55                         PAD_CTL_SRE_FAST)
  56 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  57
  58 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  59
  60 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
  61         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  62         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  63
  64 #define I2C_PMIC        1
  65
  66 int dram_init(void)
  67 {
  68         gd->ram_size = imx_ddr_size();
  69
  70         return 0;
  71 }
  72
  73 static iomux_v3_cfg_t const uart4_pads[] = {
  74         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  75         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  76 };
  77
  78 static iomux_v3_cfg_t const enet_pads[] = {
  79         IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO              | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_KEY_COL2__ENET_MDC               | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK        | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3             | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  93         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94 };
  95
  96 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  97 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
  98         .scl = {
  99                 .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
 100                 .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
 101                 .gp = IMX_GPIO_NR(2, 30)
 102         },
 103         .sda = {
 104                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 105                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 106                 .gp = IMX_GPIO_NR(4, 13)
 107         }
 108 };
 109
 110 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 111         .scl = {
 112                 .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
 113                 .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
 114                 .gp = IMX_GPIO_NR(2, 30)
 115         },
 116         .sda = {
 117                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 118                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 119                 .gp = IMX_GPIO_NR(4, 13)
 120         }
 121 };
 122
 123 #ifndef CONFIG_SYS_FLASH_CFI
 124 /*
 125  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
 126  * Compass Sensor, Accelerometer, Res Touch
 127  */
 128 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
 129         .scl = {
 130                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 131                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 132                 .gp = IMX_GPIO_NR(1, 3)
 133         },
 134         .sda = {
 135                 .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
 136                 .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
 137                 .gp = IMX_GPIO_NR(3, 18)
 138         }
 139 };
 140
 141 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 142         .scl = {
 143                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 144                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 145                 .gp = IMX_GPIO_NR(1, 3)
 146         },
 147         .sda = {
 148                 .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
 149                 .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
 150                 .gp = IMX_GPIO_NR(3, 18)
 151         }
 152 };
 153 #endif
 154
 155 static iomux_v3_cfg_t const i2c3_pads[] = {
 156         IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 157 };
 158
 159 static iomux_v3_cfg_t const port_exp[] = {
 160         IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 161 };
 162
 163 #ifdef CONFIG_MTD_NOR_FLASH
 164 static iomux_v3_cfg_t const eimnor_pads[] = {
 165         IOMUX_PADS(PAD_EIM_D16__EIM_DATA16      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 166         IOMUX_PADS(PAD_EIM_D17__EIM_DATA17      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 167         IOMUX_PADS(PAD_EIM_D18__EIM_DATA18      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 168         IOMUX_PADS(PAD_EIM_D19__EIM_DATA19      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 169         IOMUX_PADS(PAD_EIM_D20__EIM_DATA20      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 170         IOMUX_PADS(PAD_EIM_D21__EIM_DATA21      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 171         IOMUX_PADS(PAD_EIM_D22__EIM_DATA22      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 172         IOMUX_PADS(PAD_EIM_D23__EIM_DATA23      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 173         IOMUX_PADS(PAD_EIM_D24__EIM_DATA24      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 174         IOMUX_PADS(PAD_EIM_D25__EIM_DATA25      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 175         IOMUX_PADS(PAD_EIM_D26__EIM_DATA26      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 176         IOMUX_PADS(PAD_EIM_D27__EIM_DATA27      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 177         IOMUX_PADS(PAD_EIM_D28__EIM_DATA28      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 178         IOMUX_PADS(PAD_EIM_D29__EIM_DATA29      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 179         IOMUX_PADS(PAD_EIM_D30__EIM_DATA30      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 180         IOMUX_PADS(PAD_EIM_D31__EIM_DATA31      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 181         IOMUX_PADS(PAD_EIM_DA0__EIM_AD00        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 182         IOMUX_PADS(PAD_EIM_DA1__EIM_AD01        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 183         IOMUX_PADS(PAD_EIM_DA2__EIM_AD02        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 184         IOMUX_PADS(PAD_EIM_DA3__EIM_AD03        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 185         IOMUX_PADS(PAD_EIM_DA4__EIM_AD04        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 186         IOMUX_PADS(PAD_EIM_DA5__EIM_AD05        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 187         IOMUX_PADS(PAD_EIM_DA6__EIM_AD06        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 188         IOMUX_PADS(PAD_EIM_DA7__EIM_AD07        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 189         IOMUX_PADS(PAD_EIM_DA8__EIM_AD08        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 190         IOMUX_PADS(PAD_EIM_DA9__EIM_AD09        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 191         IOMUX_PADS(PAD_EIM_DA10__EIM_AD10       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 192         IOMUX_PADS(PAD_EIM_DA11__EIM_AD11       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 193         IOMUX_PADS(PAD_EIM_DA12__EIM_AD12       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 194         IOMUX_PADS(PAD_EIM_DA13__EIM_AD13       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 195         IOMUX_PADS(PAD_EIM_DA14__EIM_AD14       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 196         IOMUX_PADS(PAD_EIM_DA15__EIM_AD15       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 197         IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 198         IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 199         IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 200         IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 201         IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 202         IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 203         IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 204         IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 205         IOMUX_PADS(PAD_EIM_OE__EIM_OE_B         | MUX_PAD_CTRL(NO_PAD_CTRL)),
 206         IOMUX_PADS(PAD_EIM_RW__EIM_RW           | MUX_PAD_CTRL(NO_PAD_CTRL)),
 207         IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 208 };
 209
 210 static void eimnor_cs_setup(void)
 211 {
 212         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 213
 214         writel(0x00020181, &weim_regs->cs0gcr1);
 215         writel(0x00000001, &weim_regs->cs0gcr2);
 216         writel(0x0a020000, &weim_regs->cs0rcr1);
 217         writel(0x0000c000, &weim_regs->cs0rcr2);
 218         writel(0x0804a240, &weim_regs->cs0wcr1);
 219         writel(0x00000120, &weim_regs->wcr);
 220
 221         set_chipselect_size(CS0_128);
 222 }
 223
 224 static void eim_clk_setup(void)
 225 {
 226         struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 227         int cscmr1, ccgr6;
 228
 229
 230         /* Turn off EIM clock */
 231         ccgr6 = readl(&imx_ccm->CCGR6);
 232         ccgr6 &= ~(0x3 << 10);
 233         writel(ccgr6, &imx_ccm->CCGR6);
 234
 235         /*
 236          * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
 237          * and aclk_eim_slow_podf = 01 --> divide by 2
 238          * so that we can have EIM at the maximum clock of 132MHz
 239          */
 240         cscmr1 = readl(&imx_ccm->cscmr1);
 241         cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
 242                     MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
 243         cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
 244         writel(cscmr1, &imx_ccm->cscmr1);
 245
 246         /* Turn on EIM clock */
 247         ccgr6 |= (0x3 << 10);
 248         writel(ccgr6, &imx_ccm->CCGR6);
 249 }
 250
 251 static void setup_iomux_eimnor(void)
 252 {
 253         SETUP_IOMUX_PADS(eimnor_pads);
 254
 255         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 256
 257         eimnor_cs_setup();
 258 }
 259 #endif
 260
 261 static void setup_iomux_enet(void)
 262 {
 263         SETUP_IOMUX_PADS(enet_pads);
 264 }
 265
 266 static iomux_v3_cfg_t const usdhc3_pads[] = {
 267         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 268         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 269         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 270         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 271         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 272         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 273         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 274         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 275         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 276         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 277         IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT     | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 278         IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 279 };
 280
 281 static void setup_iomux_uart(void)
 282 {
 283         SETUP_IOMUX_PADS(uart4_pads);
 284 }
 285
 286 #ifdef CONFIG_FSL_ESDHC_IMX
 287 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 288         {USDHC3_BASE_ADDR},
 289 };
 290
 291 int board_mmc_getcd(struct mmc *mmc)
 292 {
 293         gpio_direction_input(IMX_GPIO_NR(6, 15));
 294         return !gpio_get_value(IMX_GPIO_NR(6, 15));
 295 }
 296
 297 int board_mmc_init(bd_t *bis)
 298 {
 299         SETUP_IOMUX_PADS(usdhc3_pads);
 300
 301         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 302         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 303 }
 304 #endif
 305
 306 #ifdef CONFIG_NAND_MXS
 307 static iomux_v3_cfg_t gpmi_pads[] = {
 308         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE      | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 309         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE      | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 310         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 311         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B  | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
 312         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 313         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B       | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 314         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B       | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 315         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 316         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 317         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 318         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 319         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 320         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 321         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 322         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 323         IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS       | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
 324 };
 325
 326 static void setup_gpmi_nand(void)
 327 {
 328         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 329
 330         /* config gpmi nand iomux */
 331         SETUP_IOMUX_PADS(gpmi_pads);
 332
 333         setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 334                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 335                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
 336
 337         /* enable apbh clock gating */
 338         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 339 }
 340 #endif
 341
 342 static void setup_fec(void)
 343 {
 344         if (is_mx6dqp()) {
 345                 /*
 346                  * select ENET MAC0 TX clock from PLL
 347                  */
 348                 imx_iomux_set_gpr_register(5, 9, 1, 1);
 349                 enable_fec_anatop_clock(0, ENET_125MHZ);
 350         }
 351
 352         setup_iomux_enet();
 353 }
 354
 355 int board_eth_init(bd_t *bis)
 356 {
 357         setup_fec();
 358
 359         return cpu_eth_init(bis);
 360 }
 361
 362 u32 get_board_rev(void)
 363 {
 364         int rev = nxp_board_rev();
 365
 366         return (get_cpu_rev() & ~(0xF << 8)) | rev;
 367 }
 368
 369 static int ar8031_phy_fixup(struct phy_device *phydev)
 370 {
 371         unsigned short val;
 372
 373         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 374         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 375         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 376         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 377
 378         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 379         val &= 0xffe3;
 380         val |= 0x18;
 381         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 382
 383         /* introduce tx clock delay */
 384         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 385         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 386         val |= 0x0100;
 387         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 388
 389         return 0;
 390 }
 391
 392 int board_phy_config(struct phy_device *phydev)
 393 {
 394         ar8031_phy_fixup(phydev);
 395
 396         if (phydev->drv->config)
 397                 phydev->drv->config(phydev);
 398
 399         return 0;
 400 }
 401
 402 #if defined(CONFIG_VIDEO_IPUV3)
 403 static void disable_lvds(struct display_info_t const *dev)
 404 {
 405         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 406
 407         clrbits_le32(&iomux->gpr[2],
 408                      IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 409                      IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 410 }
 411
 412 static void do_enable_hdmi(struct display_info_t const *dev)
 413 {
 414         disable_lvds(dev);
 415         imx_enable_hdmi_phy();
 416 }
 417
 418 struct display_info_t const displays[] = {{
 419         .bus    = -1,
 420         .addr   = 0,
 421         .pixfmt = IPU_PIX_FMT_RGB666,
 422         .detect = NULL,
 423         .enable = NULL,
 424         .mode   = {
 425                 .name           = "Hannstar-XGA",
 426                 .refresh        = 60,
 427                 .xres           = 1024,
 428                 .yres           = 768,
 429                 .pixclock       = 15385,
 430                 .left_margin    = 220,
 431                 .right_margin   = 40,
 432                 .upper_margin   = 21,
 433                 .lower_margin   = 7,
 434                 .hsync_len      = 60,
 435                 .vsync_len      = 10,
 436                 .sync           = FB_SYNC_EXT,
 437                 .vmode          = FB_VMODE_NONINTERLACED
 438 } }, {
 439         .bus    = -1,
 440         .addr   = 0,
 441         .pixfmt = IPU_PIX_FMT_RGB24,
 442         .detect = detect_hdmi,
 443         .enable = do_enable_hdmi,
 444         .mode   = {
 445                 .name           = "HDMI",
 446                 .refresh        = 60,
 447                 .xres           = 1024,
 448                 .yres           = 768,
 449                 .pixclock       = 15385,
 450                 .left_margin    = 220,
 451                 .right_margin   = 40,
 452                 .upper_margin   = 21,
 453                 .lower_margin   = 7,
 454                 .hsync_len      = 60,
 455                 .vsync_len      = 10,
 456                 .sync           = FB_SYNC_EXT,
 457                 .vmode          = FB_VMODE_NONINTERLACED,
 458 } } };
 459 size_t display_count = ARRAY_SIZE(displays);
 460
 461 iomux_v3_cfg_t const backlight_pads[] = {
 462         IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 463 };
 464
 465 static void setup_iomux_backlight(void)
 466 {
 467         gpio_request(IMX_GPIO_NR(2, 9), "backlight");
 468         gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
 469         SETUP_IOMUX_PADS(backlight_pads);
 470 }
 471
 472 static void setup_display(void)
 473 {
 474         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 475         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 476         int reg;
 477
 478         setup_iomux_backlight();
 479         enable_ipu_clock();
 480         imx_setup_hdmi();
 481
 482         /* Turn on LDB_DI0 and LDB_DI1 clocks */
 483         reg = readl(&mxc_ccm->CCGR3);
 484         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 485         writel(reg, &mxc_ccm->CCGR3);
 486
 487         /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
 488         reg = readl(&mxc_ccm->cs2cdr);
 489         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 490                  MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 491         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 492                (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 493         writel(reg, &mxc_ccm->cs2cdr);
 494
 495         reg = readl(&mxc_ccm->cscmr2);
 496         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 497         writel(reg, &mxc_ccm->cscmr2);
 498
 499         reg = readl(&mxc_ccm->chsccdr);
 500         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 501                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 502         reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
 503                 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 504         writel(reg, &mxc_ccm->chsccdr);
 505
 506         reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 507               IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 508               IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 509               IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
 510               IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 511               IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
 512               IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 513               IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
 514         writel(reg, &iomux->gpr[2]);
 515
 516         reg = readl(&iomux->gpr[3]);
 517         reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 518                  IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 519         reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 520                 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
 521                (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 522                 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
 523         writel(reg, &iomux->gpr[3]);
 524 }
 525 #endif /* CONFIG_VIDEO_IPUV3 */
 526
 527 /*
 528  * Do not overwrite the console
 529  * Use always serial for U-Boot console
 530  */
 531 int overwrite_console(void)
 532 {
 533         return 1;
 534 }
 535
 536 int board_early_init_f(void)
 537 {
 538         setup_iomux_uart();
 539
 540 #ifdef CONFIG_NAND_MXS
 541         setup_gpmi_nand();
 542 #endif
 543
 544 #ifdef CONFIG_MTD_NOR_FLASH
 545         eim_clk_setup();
 546 #endif
 547         return 0;
 548 }
 549
 550 int board_init(void)
 551 {
 552         /* address of boot parameters */
 553         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 554
 555         /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
 556         if (is_mx6dq() || is_mx6dqp())
 557                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 558         else
 559                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 560         /* I2C 3 Steer */
 561         gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
 562         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 563         SETUP_IOMUX_PADS(i2c3_pads);
 564 #ifndef CONFIG_SYS_FLASH_CFI
 565         if (is_mx6dq() || is_mx6dqp())
 566                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
 567         else
 568                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
 569 #endif
 570         gpio_request(IMX_GPIO_NR(1, 15), "expander en");
 571         gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 572         SETUP_IOMUX_PADS(port_exp);
 573
 574 #ifdef CONFIG_VIDEO_IPUV3
 575         setup_display();
 576 #endif
 577
 578 #ifdef CONFIG_MTD_NOR_FLASH
 579         setup_iomux_eimnor();
 580 #endif
 581         return 0;
 582 }
 583
 584 #ifdef CONFIG_MXC_SPI
 585 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 586 {
 587         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 588 }
 589 #endif
 590
 591 int power_init_board(void)
 592 {
 593         struct pmic *p;
 594         unsigned int value;
 595
 596         p = pfuze_common_init(I2C_PMIC);
 597         if (!p)
 598                 return -ENODEV;
 599
 600         if (is_mx6dqp()) {
 601                 /* set SW2 staby volatage 0.975V*/
 602                 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
 603                 value &= ~0x3f;
 604                 value |= 0x17;
 605                 pmic_reg_write(p, PFUZE100_SW2STBY, value);
 606         }
 607
 608         return pfuze_mode_init(p, APS_PFM);
 609 }
 610
 611 #ifdef CONFIG_CMD_BMODE
 612 static const struct boot_mode board_boot_modes[] = {
 613         /* 4 bit bus width */
 614         {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 615         {NULL,   0},
 616 };
 617 #endif
 618
 619 int board_late_init(void)
 620 {
 621 #ifdef CONFIG_CMD_BMODE
 622         add_board_boot_modes(board_boot_modes);
 623 #endif
 624
 625 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 626         env_set("board_name", "SABREAUTO");
 627
 628         if (is_mx6dqp())
 629                 env_set("board_rev", "MX6QP");
 630         else if (is_mx6dq())
 631                 env_set("board_rev", "MX6Q");
 632         else if (is_mx6sdl())
 633                 env_set("board_rev", "MX6DL");
 634 #endif
 635
 636         return 0;
 637 }
 638
 639 int checkboard(void)
 640 {
 641         printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
 642
 643         return 0;
 644 }
 645
 646 #ifdef CONFIG_USB_EHCI_MX6
 647 int board_ehci_hcd_init(int port)
 648 {
 649         switch (port) {
 650         case 0:
 651                 /*
 652                   * Set daisy chain for otg_pin_id on 6q.
 653                  *  For 6dl, this bit is reserved.
 654                  */
 655                 imx_iomux_set_gpr_register(1, 13, 1, 0);
 656                 break;
 657         case 1:
 658                 break;
 659         default:
 660                 printf("MXC USB port %d not yet supported\n", port);
 661                 return -EINVAL;
 662         }
 663         return 0;
 664 }
 665 #endif
 666
 667 #ifdef CONFIG_SPL_BUILD
 668 #include <asm/arch/mx6-ddr.h>
 669 #include <spl.h>
 670 #include <linux/libfdt.h>
 671
 672 #ifdef CONFIG_SPL_OS_BOOT
 673 int spl_start_uboot(void)
 674 {
 675         return 0;
 676 }
 677 #endif
 678
 679 static void ccgr_init(void)
 680 {
 681         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 682
 683         writel(0x00C03F3F, &ccm->CCGR0);
 684         writel(0x0030FC03, &ccm->CCGR1);
 685         writel(0x0FFFC000, &ccm->CCGR2);
 686         writel(0x3FF00000, &ccm->CCGR3);
 687         writel(0x00FFF300, &ccm->CCGR4);
 688         writel(0x0F0000C3, &ccm->CCGR5);
 689         writel(0x000003FF, &ccm->CCGR6);
 690 }
 691
 692 static int mx6q_dcd_table[] = {
 693         0x020e0798, 0x000C0000,
 694         0x020e0758, 0x00000000,
 695         0x020e0588, 0x00000030,
 696         0x020e0594, 0x00000030,
 697         0x020e056c, 0x00000030,
 698         0x020e0578, 0x00000030,
 699         0x020e074c, 0x00000030,
 700         0x020e057c, 0x00000030,
 701         0x020e058c, 0x00000000,
 702         0x020e059c, 0x00000030,
 703         0x020e05a0, 0x00000030,
 704         0x020e078c, 0x00000030,
 705         0x020e0750, 0x00020000,
 706         0x020e05a8, 0x00000028,
 707         0x020e05b0, 0x00000028,
 708         0x020e0524, 0x00000028,
 709         0x020e051c, 0x00000028,
 710         0x020e0518, 0x00000028,
 711         0x020e050c, 0x00000028,
 712         0x020e05b8, 0x00000028,
 713         0x020e05c0, 0x00000028,
 714         0x020e0774, 0x00020000,
 715         0x020e0784, 0x00000028,
 716         0x020e0788, 0x00000028,
 717         0x020e0794, 0x00000028,
 718         0x020e079c, 0x00000028,
 719         0x020e07a0, 0x00000028,
 720         0x020e07a4, 0x00000028,
 721         0x020e07a8, 0x00000028,
 722         0x020e0748, 0x00000028,
 723         0x020e05ac, 0x00000028,
 724         0x020e05b4, 0x00000028,
 725         0x020e0528, 0x00000028,
 726         0x020e0520, 0x00000028,
 727         0x020e0514, 0x00000028,
 728         0x020e0510, 0x00000028,
 729         0x020e05bc, 0x00000028,
 730         0x020e05c4, 0x00000028,
 731         0x021b0800, 0xa1390003,
 732         0x021b080c, 0x001F001F,
 733         0x021b0810, 0x001F001F,
 734         0x021b480c, 0x001F001F,
 735         0x021b4810, 0x001F001F,
 736         0x021b083c, 0x43260335,
 737         0x021b0840, 0x031A030B,
 738         0x021b483c, 0x4323033B,
 739         0x021b4840, 0x0323026F,
 740         0x021b0848, 0x483D4545,
 741         0x021b4848, 0x44433E48,
 742         0x021b0850, 0x41444840,
 743         0x021b4850, 0x4835483E,
 744         0x021b081c, 0x33333333,
 745         0x021b0820, 0x33333333,
 746         0x021b0824, 0x33333333,
 747         0x021b0828, 0x33333333,
 748         0x021b481c, 0x33333333,
 749         0x021b4820, 0x33333333,
 750         0x021b4824, 0x33333333,
 751         0x021b4828, 0x33333333,
 752         0x021b08b8, 0x00000800,
 753         0x021b48b8, 0x00000800,
 754         0x021b0004, 0x00020036,
 755         0x021b0008, 0x09444040,
 756         0x021b000c, 0x8A8F7955,
 757         0x021b0010, 0xFF328F64,
 758         0x021b0014, 0x01FF00DB,
 759         0x021b0018, 0x00001740,
 760         0x021b001c, 0x00008000,
 761         0x021b002c, 0x000026d2,
 762         0x021b0030, 0x008F1023,
 763         0x021b0040, 0x00000047,
 764         0x021b0000, 0x841A0000,
 765         0x021b001c, 0x04088032,
 766         0x021b001c, 0x00008033,
 767         0x021b001c, 0x00048031,
 768         0x021b001c, 0x09408030,
 769         0x021b001c, 0x04008040,
 770         0x021b0020, 0x00005800,
 771         0x021b0818, 0x00011117,
 772         0x021b4818, 0x00011117,
 773         0x021b0004, 0x00025576,
 774         0x021b0404, 0x00011006,
 775         0x021b001c, 0x00000000,
 776         0x020c4068, 0x00C03F3F,
 777         0x020c406c, 0x0030FC03,
 778         0x020c4070, 0x0FFFC000,
 779         0x020c4074, 0x3FF00000,
 780         0x020c4078, 0xFFFFF300,
 781         0x020c407c, 0x0F0000F3,
 782         0x020c4080, 0x00000FFF,
 783         0x020e0010, 0xF00000CF,
 784         0x020e0018, 0x007F007F,
 785         0x020e001c, 0x007F007F,
 786 };
 787
 788 static int mx6qp_dcd_table[] = {
 789         0x020e0798, 0x000C0000,
 790         0x020e0758, 0x00000000,
 791         0x020e0588, 0x00000030,
 792         0x020e0594, 0x00000030,
 793         0x020e056c, 0x00000030,
 794         0x020e0578, 0x00000030,
 795         0x020e074c, 0x00000030,
 796         0x020e057c, 0x00000030,
 797         0x020e058c, 0x00000000,
 798         0x020e059c, 0x00000030,
 799         0x020e05a0, 0x00000030,
 800         0x020e078c, 0x00000030,
 801         0x020e0750, 0x00020000,
 802         0x020e05a8, 0x00000030,
 803         0x020e05b0, 0x00000030,
 804         0x020e0524, 0x00000030,
 805         0x020e051c, 0x00000030,
 806         0x020e0518, 0x00000030,
 807         0x020e050c, 0x00000030,
 808         0x020e05b8, 0x00000030,
 809         0x020e05c0, 0x00000030,
 810         0x020e0774, 0x00020000,
 811         0x020e0784, 0x00000030,
 812         0x020e0788, 0x00000030,
 813         0x020e0794, 0x00000030,
 814         0x020e079c, 0x00000030,
 815         0x020e07a0, 0x00000030,
 816         0x020e07a4, 0x00000030,
 817         0x020e07a8, 0x00000030,
 818         0x020e0748, 0x00000030,
 819         0x020e05ac, 0x00000030,
 820         0x020e05b4, 0x00000030,
 821         0x020e0528, 0x00000030,
 822         0x020e0520, 0x00000030,
 823         0x020e0514, 0x00000030,
 824         0x020e0510, 0x00000030,
 825         0x020e05bc, 0x00000030,
 826         0x020e05c4, 0x00000030,
 827         0x021b0800, 0xa1390003,
 828         0x021b080c, 0x001b001e,
 829         0x021b0810, 0x002e0029,
 830         0x021b480c, 0x001b002a,
 831         0x021b4810, 0x0019002c,
 832         0x021b083c, 0x43240334,
 833         0x021b0840, 0x0324031a,
 834         0x021b483c, 0x43340344,
 835         0x021b4840, 0x03280276,
 836         0x021b0848, 0x44383A3E,
 837         0x021b4848, 0x3C3C3846,
 838         0x021b0850, 0x2e303230,
 839         0x021b4850, 0x38283E34,
 840         0x021b081c, 0x33333333,
 841         0x021b0820, 0x33333333,
 842         0x021b0824, 0x33333333,
 843         0x021b0828, 0x33333333,
 844         0x021b481c, 0x33333333,
 845         0x021b4820, 0x33333333,
 846         0x021b4824, 0x33333333,
 847         0x021b4828, 0x33333333,
 848         0x021b08c0, 0x24912492,
 849         0x021b48c0, 0x24912492,
 850         0x021b08b8, 0x00000800,
 851         0x021b48b8, 0x00000800,
 852         0x021b0004, 0x00020036,
 853         0x021b0008, 0x09444040,
 854         0x021b000c, 0x898E7955,
 855         0x021b0010, 0xFF328F64,
 856         0x021b0014, 0x01FF00DB,
 857         0x021b0018, 0x00001740,
 858         0x021b001c, 0x00008000,
 859         0x021b002c, 0x000026d2,
 860         0x021b0030, 0x008E1023,
 861         0x021b0040, 0x00000047,
 862         0x021b0400, 0x14420000,
 863         0x021b0000, 0x841A0000,
 864         0x00bb0008, 0x00000004,
 865         0x00bb000c, 0x2891E41A,
 866         0x00bb0038, 0x00000564,
 867         0x00bb0014, 0x00000040,
 868         0x00bb0028, 0x00000020,
 869         0x00bb002c, 0x00000020,
 870         0x021b001c, 0x04088032,
 871         0x021b001c, 0x00008033,
 872         0x021b001c, 0x00048031,
 873         0x021b001c, 0x09408030,
 874         0x021b001c, 0x04008040,
 875         0x021b0020, 0x00005800,
 876         0x021b0818, 0x00011117,
 877         0x021b4818, 0x00011117,
 878         0x021b0004, 0x00025576,
 879         0x021b0404, 0x00011006,
 880         0x021b001c, 0x00000000,
 881         0x020c4068, 0x00C03F3F,
 882         0x020c406c, 0x0030FC03,
 883         0x020c4070, 0x0FFFC000,
 884         0x020c4074, 0x3FF00000,
 885         0x020c4078, 0xFFFFF300,
 886         0x020c407c, 0x0F0000F3,
 887         0x020c4080, 0x00000FFF,
 888         0x020e0010, 0xF00000CF,
 889         0x020e0018, 0x77177717,
 890         0x020e001c, 0x77177717,
 891 };
 892
 893 static int mx6dl_dcd_table[] = {
 894         0x020e0774, 0x000C0000,
 895         0x020e0754, 0x00000000,
 896         0x020e04ac, 0x00000030,
 897         0x020e04b0, 0x00000030,
 898         0x020e0464, 0x00000030,
 899         0x020e0490, 0x00000030,
 900         0x020e074c, 0x00000030,
 901         0x020e0494, 0x00000030,
 902         0x020e04a0, 0x00000000,
 903         0x020e04b4, 0x00000030,
 904         0x020e04b8, 0x00000030,
 905         0x020e076c, 0x00000030,
 906         0x020e0750, 0x00020000,
 907         0x020e04bc, 0x00000028,
 908         0x020e04c0, 0x00000028,
 909         0x020e04c4, 0x00000028,
 910         0x020e04c8, 0x00000028,
 911         0x020e04cc, 0x00000028,
 912         0x020e04d0, 0x00000028,
 913         0x020e04d4, 0x00000028,
 914         0x020e04d8, 0x00000028,
 915         0x020e0760, 0x00020000,
 916         0x020e0764, 0x00000028,
 917         0x020e0770, 0x00000028,
 918         0x020e0778, 0x00000028,
 919         0x020e077c, 0x00000028,
 920         0x020e0780, 0x00000028,
 921         0x020e0784, 0x00000028,
 922         0x020e078c, 0x00000028,
 923         0x020e0748, 0x00000028,
 924         0x020e0470, 0x00000028,
 925         0x020e0474, 0x00000028,
 926         0x020e0478, 0x00000028,
 927         0x020e047c, 0x00000028,
 928         0x020e0480, 0x00000028,
 929         0x020e0484, 0x00000028,
 930         0x020e0488, 0x00000028,
 931         0x020e048c, 0x00000028,
 932         0x021b0800, 0xa1390003,
 933         0x021b080c, 0x001F001F,
 934         0x021b0810, 0x001F001F,
 935         0x021b480c, 0x001F001F,
 936         0x021b4810, 0x001F001F,
 937         0x021b083c, 0x42190217,
 938         0x021b0840, 0x017B017B,
 939         0x021b483c, 0x4176017B,
 940         0x021b4840, 0x015F016C,
 941         0x021b0848, 0x4C4C4D4C,
 942         0x021b4848, 0x4A4D4C48,
 943         0x021b0850, 0x3F3F3F40,
 944         0x021b4850, 0x3538382E,
 945         0x021b081c, 0x33333333,
 946         0x021b0820, 0x33333333,
 947         0x021b0824, 0x33333333,
 948         0x021b0828, 0x33333333,
 949         0x021b481c, 0x33333333,
 950         0x021b4820, 0x33333333,
 951         0x021b4824, 0x33333333,
 952         0x021b4828, 0x33333333,
 953         0x021b08b8, 0x00000800,
 954         0x021b48b8, 0x00000800,
 955         0x021b0004, 0x00020025,
 956         0x021b0008, 0x00333030,
 957         0x021b000c, 0x676B5313,
 958         0x021b0010, 0xB66E8B63,
 959         0x021b0014, 0x01FF00DB,
 960         0x021b0018, 0x00001740,
 961         0x021b001c, 0x00008000,
 962         0x021b002c, 0x000026d2,
 963         0x021b0030, 0x006B1023,
 964         0x021b0040, 0x00000047,
 965         0x021b0000, 0x841A0000,
 966         0x021b001c, 0x04008032,
 967         0x021b001c, 0x00008033,
 968         0x021b001c, 0x00048031,
 969         0x021b001c, 0x05208030,
 970         0x021b001c, 0x04008040,
 971         0x021b0020, 0x00005800,
 972         0x021b0818, 0x00011117,
 973         0x021b4818, 0x00011117,
 974         0x021b0004, 0x00025565,
 975         0x021b0404, 0x00011006,
 976         0x021b001c, 0x00000000,
 977         0x020c4068, 0x00C03F3F,
 978         0x020c406c, 0x0030FC03,
 979         0x020c4070, 0x0FFFC000,
 980         0x020c4074, 0x3FF00000,
 981         0x020c4078, 0xFFFFF300,
 982         0x020c407c, 0x0F0000C3,
 983         0x020c4080, 0x00000FFF,
 984         0x020e0010, 0xF00000CF,
 985         0x020e0018, 0x007F007F,
 986         0x020e001c, 0x007F007F,
 987 };
 988
 989 static void ddr_init(int *table, int size)
 990 {
 991         int i;
 992
 993         for (i = 0; i < size / 2 ; i++)
 994                 writel(table[2 * i + 1], table[2 * i]);
 995 }
 996
 997 static void spl_dram_init(void)
 998 {
 999         if (is_mx6dq())
1000                 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
1001         else if (is_mx6dqp())
1002                 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
1003         else if (is_mx6sdl())
1004                 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1005 }
1006
1007 void board_init_f(ulong dummy)
1008 {
1009         /* DDR initialization */
1010         spl_dram_init();
1011
1012         /* setup AIPS and disable watchdog */
1013         arch_cpu_init();
1014
1015         ccgr_init();
1016         gpr_init();
1017
1018         /* iomux and setup of i2c */
1019         board_early_init_f();
1020
1021         /* setup GP timer */
1022         timer_init();
1023
1024         /* UART clocks enabled and gd valid - init serial console */
1025         preloader_console_init();
1026
1027         /* Clear the BSS. */
1028         memset(__bss_start, 0, __bss_end - __bss_start);
1029
1030         /* load/boot image from boot device */
1031         board_init_r(NULL, 0);
1032 }
1033 #endif
1034
1035 #ifdef CONFIG_SPL_LOAD_FIT
1036 int board_fit_config_name_match(const char *name)
1037 {
1038         if (is_mx6dq()) {
1039                 if (!strcmp(name, "imx6q-sabreauto"))
1040                         return 0;
1041         } else if (is_mx6dqp()) {
1042                 if (!strcmp(name, "imx6qp-sabreauto"))
1043                         return 0;
1044         } else if (is_mx6dl()) {
1045                 if (!strcmp(name, "imx6dl-sabreauto"))
1046                         return 0;
1047         }
1048
1049         return -1;
1050 }
1051 #endif