board/freescale/mx51evk/mx51evk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <asm/io.h>
   9 #include <asm/gpio.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux-mx51.h>
  12 #include <linux/delay.h>
  13 #include <linux/errno.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/mach-imx/mx5_video.h>
  18 #include <i2c.h>
  19 #include <input.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <power/pmic.h>
  23 #include <fsl_pmic.h>
  24 #include <mc13892.h>
  25 #include <usb/ehci-ci.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_FSL_ESDHC_IMX
  30 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  31         {MMC_SDHC1_BASE_ADDR},
  32         {MMC_SDHC2_BASE_ADDR},
  33 };
  34 #endif
  35
  36 int dram_init(void)
  37 {
  38         /* dram_init must store complete ramsize in gd->ram_size */
  39         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  40                                 PHYS_SDRAM_1_SIZE);
  41         return 0;
  42 }
  43
  44 u32 get_board_rev(void)
  45 {
  46         u32 rev = get_cpu_rev();
  47         if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  48                 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  49         return rev;
  50 }
  51
  52 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
  53
  54 static void setup_iomux_uart(void)
  55 {
  56         static const iomux_v3_cfg_t uart_pads[] = {
  57                 MX51_PAD_UART1_RXD__UART1_RXD,
  58                 MX51_PAD_UART1_TXD__UART1_TXD,
  59                 NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
  60                 NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
  61         };
  62
  63         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  64 }
  65
  66 static void setup_iomux_fec(void)
  67 {
  68         static const iomux_v3_cfg_t fec_pads[] = {
  69                 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
  70                                 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
  71                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  72                 MX51_PAD_NANDF_CS3__FEC_MDC,
  73                 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
  74                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
  75                 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
  76                 MX51_PAD_NANDF_D9__FEC_RDATA0,
  77                 MX51_PAD_NANDF_CS6__FEC_TDATA3,
  78                 MX51_PAD_NANDF_CS5__FEC_TDATA2,
  79                 MX51_PAD_NANDF_CS4__FEC_TDATA1,
  80                 MX51_PAD_NANDF_D8__FEC_TDATA0,
  81                 MX51_PAD_NANDF_CS7__FEC_TX_EN,
  82                 MX51_PAD_NANDF_CS2__FEC_TX_ER,
  83                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
  84                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
  85                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
  86                 MX51_PAD_EIM_CS5__FEC_CRS,
  87                 MX51_PAD_EIM_CS4__FEC_RX_ER,
  88                 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
  89         };
  90
  91         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  92 }
  93
  94 #ifdef CONFIG_MXC_SPI
  95 static void setup_iomux_spi(void)
  96 {
  97         static const iomux_v3_cfg_t spi_pads[] = {
  98                 NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
  99                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
 100                 NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
 101                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
 102                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
 103                                 MX51_GPIO_PAD_CTRL),
 104                 MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
 105                 NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
 106                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
 107                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
 108         };
 109
 110         imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 111 }
 112 #endif
 113
 114 #ifdef CONFIG_USB_EHCI_MX5
 115 #define MX51EVK_USBH1_HUB_RST   IMX_GPIO_NR(1, 7)
 116 #define MX51EVK_USBH1_STP       IMX_GPIO_NR(1, 27)
 117 #define MX51EVK_USB_CLK_EN_B    IMX_GPIO_NR(2, 1)
 118 #define MX51EVK_USB_PHY_RESET   IMX_GPIO_NR(2, 5)
 119
 120 static void setup_usb_h1(void)
 121 {
 122         static const iomux_v3_cfg_t usb_h1_pads[] = {
 123                 MX51_PAD_USBH1_CLK__USBH1_CLK,
 124                 MX51_PAD_USBH1_DIR__USBH1_DIR,
 125                 MX51_PAD_USBH1_STP__USBH1_STP,
 126                 MX51_PAD_USBH1_NXT__USBH1_NXT,
 127                 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
 128                 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
 129                 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
 130                 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
 131                 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
 132                 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
 133                 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
 134                 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 135
 136                 NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
 137                 MX51_PAD_EIM_D17__GPIO2_1,
 138                 MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
 139         };
 140
 141         imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
 142 }
 143
 144 int board_ehci_hcd_init(int port)
 145 {
 146         /* Set USBH1_STP to GPIO and toggle it */
 147         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
 148                                                 MX51_USBH_PAD_CTRL));
 149
 150         gpio_direction_output(MX51EVK_USBH1_STP, 0);
 151         gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
 152         mdelay(10);
 153         gpio_set_value(MX51EVK_USBH1_STP, 1);
 154
 155         /* Set back USBH1_STP to be function */
 156         imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
 157
 158         /* De-assert USB PHY RESETB */
 159         gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
 160
 161         /* Drive USB_CLK_EN_B line low */
 162         gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
 163
 164         /* Reset USB hub */
 165         gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
 166         mdelay(2);
 167         gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
 168         return 0;
 169 }
 170 #endif
 171
 172 static void power_init(void)
 173 {
 174         unsigned int val;
 175         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 176         struct pmic *p;
 177         int ret;
 178
 179         ret = pmic_init(CONFIG_FSL_PMIC_BUS);
 180         if (ret)
 181                 return;
 182
 183         p = pmic_get("FSL_PMIC");
 184         if (!p)
 185                 return;
 186
 187         /* Write needed to Power Gate 2 register */
 188         pmic_reg_read(p, REG_POWER_MISC, &val);
 189         val &= ~PWGT2SPIEN;
 190         pmic_reg_write(p, REG_POWER_MISC, val);
 191
 192         /* Externally powered */
 193         pmic_reg_read(p, REG_CHARGE, &val);
 194         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
 195         pmic_reg_write(p, REG_CHARGE, val);
 196
 197         /* power up the system first */
 198         pmic_reg_write(p, REG_POWER_MISC, PWUP);
 199
 200         /* Set core voltage to 1.1V */
 201         pmic_reg_read(p, REG_SW_0, &val);
 202         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
 203         pmic_reg_write(p, REG_SW_0, val);
 204
 205         /* Setup VCC (SW2) to 1.25 */
 206         pmic_reg_read(p, REG_SW_1, &val);
 207         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 208         pmic_reg_write(p, REG_SW_1, val);
 209
 210         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 211         pmic_reg_read(p, REG_SW_2, &val);
 212         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 213         pmic_reg_write(p, REG_SW_2, val);
 214         udelay(50);
 215
 216         /* Raise the core frequency to 800MHz */
 217         writel(0x0, &mxc_ccm->cacrr);
 218
 219         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 220         /* Setup the switcher mode for SW1 & SW2*/
 221         pmic_reg_read(p, REG_SW_4, &val);
 222         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 223                 (SWMODE_MASK << SWMODE2_SHIFT)));
 224         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 225                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 226         pmic_reg_write(p, REG_SW_4, val);
 227
 228         /* Setup the switcher mode for SW3 & SW4 */
 229         pmic_reg_read(p, REG_SW_5, &val);
 230         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 231                 (SWMODE_MASK << SWMODE4_SHIFT)));
 232         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 233                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 234         pmic_reg_write(p, REG_SW_5, val);
 235
 236         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
 237         pmic_reg_read(p, REG_SETTING_0, &val);
 238         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 239         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
 240         pmic_reg_write(p, REG_SETTING_0, val);
 241
 242         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 243         pmic_reg_read(p, REG_SETTING_1, &val);
 244         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 245         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
 246         pmic_reg_write(p, REG_SETTING_1, val);
 247
 248         /* Configure VGEN3 and VCAM regulators to use external PNP */
 249         val = VGEN3CONFIG | VCAMCONFIG;
 250         pmic_reg_write(p, REG_MODE_1, val);
 251         udelay(200);
 252
 253         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 254         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 255                 VVIDEOEN | VAUDIOEN  | VSDEN;
 256         pmic_reg_write(p, REG_MODE_1, val);
 257
 258         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
 259                                                 NO_PAD_CTRL));
 260         gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
 261
 262         udelay(500);
 263
 264         gpio_set_value(IMX_GPIO_NR(2, 14), 1);
 265 }
 266
 267 #ifdef CONFIG_FSL_ESDHC_IMX
 268 int board_mmc_getcd(struct mmc *mmc)
 269 {
 270         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 271         int ret;
 272
 273         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
 274                                                 NO_PAD_CTRL));
 275         gpio_direction_input(IMX_GPIO_NR(1, 0));
 276         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
 277                                                 NO_PAD_CTRL));
 278         gpio_direction_input(IMX_GPIO_NR(1, 6));
 279
 280         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 281                 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
 282         else
 283                 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
 284
 285         return ret;
 286 }
 287
 288 int board_mmc_init(bd_t *bis)
 289 {
 290         static const iomux_v3_cfg_t sd1_pads[] = {
 291                 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
 292                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 293                 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
 294                         PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 295                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
 296                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 297                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
 298                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 299                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
 300                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 301                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
 302                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
 303                 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
 304                 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
 305         };
 306
 307         static const iomux_v3_cfg_t sd2_pads[] = {
 308                 NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
 309                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 310                 NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
 311                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 312                 NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
 313                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 314                 NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
 315                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 316                 NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
 317                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 318                 NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
 319                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 320                 NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
 321                 NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
 322         };
 323
 324         u32 index;
 325         int ret;
 326
 327         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 328         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 329
 330         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 331                         index++) {
 332                 switch (index) {
 333                 case 0:
 334                         imx_iomux_v3_setup_multiple_pads(sd1_pads,
 335                                                          ARRAY_SIZE(sd1_pads));
 336                         break;
 337                 case 1:
 338                         imx_iomux_v3_setup_multiple_pads(sd2_pads,
 339                                                          ARRAY_SIZE(sd2_pads));
 340                         break;
 341                 default:
 342                         printf("Warning: you configured more ESDHC controller"
 343                                 "(%d) as supported by the board(2)\n",
 344                                 CONFIG_SYS_FSL_ESDHC_NUM);
 345                         return -EINVAL;
 346                 }
 347                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 348                 if (ret)
 349                         return ret;
 350         }
 351         return 0;
 352 }
 353 #endif
 354
 355 int board_early_init_f(void)
 356 {
 357         setup_iomux_uart();
 358         setup_iomux_fec();
 359 #ifdef CONFIG_USB_EHCI_MX5
 360         setup_usb_h1();
 361 #endif
 362         setup_iomux_lcd();
 363
 364         return 0;
 365 }
 366
 367 int board_init(void)
 368 {
 369         /* address of boot parameters */
 370         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 371
 372         return 0;
 373 }
 374
 375 #ifdef CONFIG_BOARD_LATE_INIT
 376 int board_late_init(void)
 377 {
 378 #ifdef CONFIG_MXC_SPI
 379         setup_iomux_spi();
 380         power_init();
 381 #endif
 382
 383         return 0;
 384 }
 385 #endif
 386
 387 /*
 388  * Do not overwrite the console
 389  * Use always serial for U-Boot console
 390  */
 391 int overwrite_console(void)
 392 {
 393         return 1;
 394 }
 395
 396 int checkboard(void)
 397 {
 398         puts("Board: MX51EVK\n");
 399
 400         return 0;
 401 }