board/freescale/mx51evk/mx51evk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <asm/io.h>
   9 #include <asm/gpio.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux-mx51.h>
  12 #include <linux/errno.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/mach-imx/mx5_video.h>
  17 #include <i2c.h>
  18 #include <input.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc_imx.h>
  21 #include <power/pmic.h>
  22 #include <fsl_pmic.h>
  23 #include <mc13892.h>
  24 #include <usb/ehci-ci.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #ifdef CONFIG_FSL_ESDHC_IMX
  29 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  30         {MMC_SDHC1_BASE_ADDR},
  31         {MMC_SDHC2_BASE_ADDR},
  32 };
  33 #endif
  34
  35 int dram_init(void)
  36 {
  37         /* dram_init must store complete ramsize in gd->ram_size */
  38         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  39                                 PHYS_SDRAM_1_SIZE);
  40         return 0;
  41 }
  42
  43 u32 get_board_rev(void)
  44 {
  45         u32 rev = get_cpu_rev();
  46         if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  47                 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  48         return rev;
  49 }
  50
  51 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
  52
  53 static void setup_iomux_uart(void)
  54 {
  55         static const iomux_v3_cfg_t uart_pads[] = {
  56                 MX51_PAD_UART1_RXD__UART1_RXD,
  57                 MX51_PAD_UART1_TXD__UART1_TXD,
  58                 NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
  59                 NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
  60         };
  61
  62         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  63 }
  64
  65 static void setup_iomux_fec(void)
  66 {
  67         static const iomux_v3_cfg_t fec_pads[] = {
  68                 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
  69                                 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
  70                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  71                 MX51_PAD_NANDF_CS3__FEC_MDC,
  72                 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
  73                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
  74                 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
  75                 MX51_PAD_NANDF_D9__FEC_RDATA0,
  76                 MX51_PAD_NANDF_CS6__FEC_TDATA3,
  77                 MX51_PAD_NANDF_CS5__FEC_TDATA2,
  78                 MX51_PAD_NANDF_CS4__FEC_TDATA1,
  79                 MX51_PAD_NANDF_D8__FEC_TDATA0,
  80                 MX51_PAD_NANDF_CS7__FEC_TX_EN,
  81                 MX51_PAD_NANDF_CS2__FEC_TX_ER,
  82                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
  83                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
  84                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
  85                 MX51_PAD_EIM_CS5__FEC_CRS,
  86                 MX51_PAD_EIM_CS4__FEC_RX_ER,
  87                 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
  88         };
  89
  90         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  91 }
  92
  93 #ifdef CONFIG_MXC_SPI
  94 static void setup_iomux_spi(void)
  95 {
  96         static const iomux_v3_cfg_t spi_pads[] = {
  97                 NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
  98                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  99                 NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
 100                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
 101                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
 102                                 MX51_GPIO_PAD_CTRL),
 103                 MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
 104                 NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
 105                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
 106                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
 107         };
 108
 109         imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 110 }
 111 #endif
 112
 113 #ifdef CONFIG_USB_EHCI_MX5
 114 #define MX51EVK_USBH1_HUB_RST   IMX_GPIO_NR(1, 7)
 115 #define MX51EVK_USBH1_STP       IMX_GPIO_NR(1, 27)
 116 #define MX51EVK_USB_CLK_EN_B    IMX_GPIO_NR(2, 1)
 117 #define MX51EVK_USB_PHY_RESET   IMX_GPIO_NR(2, 5)
 118
 119 static void setup_usb_h1(void)
 120 {
 121         static const iomux_v3_cfg_t usb_h1_pads[] = {
 122                 MX51_PAD_USBH1_CLK__USBH1_CLK,
 123                 MX51_PAD_USBH1_DIR__USBH1_DIR,
 124                 MX51_PAD_USBH1_STP__USBH1_STP,
 125                 MX51_PAD_USBH1_NXT__USBH1_NXT,
 126                 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
 127                 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
 128                 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
 129                 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
 130                 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
 131                 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
 132                 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
 133                 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 134
 135                 NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
 136                 MX51_PAD_EIM_D17__GPIO2_1,
 137                 MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
 138         };
 139
 140         imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
 141 }
 142
 143 int board_ehci_hcd_init(int port)
 144 {
 145         /* Set USBH1_STP to GPIO and toggle it */
 146         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
 147                                                 MX51_USBH_PAD_CTRL));
 148
 149         gpio_direction_output(MX51EVK_USBH1_STP, 0);
 150         gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
 151         mdelay(10);
 152         gpio_set_value(MX51EVK_USBH1_STP, 1);
 153
 154         /* Set back USBH1_STP to be function */
 155         imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
 156
 157         /* De-assert USB PHY RESETB */
 158         gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
 159
 160         /* Drive USB_CLK_EN_B line low */
 161         gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
 162
 163         /* Reset USB hub */
 164         gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
 165         mdelay(2);
 166         gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
 167         return 0;
 168 }
 169 #endif
 170
 171 static void power_init(void)
 172 {
 173         unsigned int val;
 174         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 175         struct pmic *p;
 176         int ret;
 177
 178         ret = pmic_init(CONFIG_FSL_PMIC_BUS);
 179         if (ret)
 180                 return;
 181
 182         p = pmic_get("FSL_PMIC");
 183         if (!p)
 184                 return;
 185
 186         /* Write needed to Power Gate 2 register */
 187         pmic_reg_read(p, REG_POWER_MISC, &val);
 188         val &= ~PWGT2SPIEN;
 189         pmic_reg_write(p, REG_POWER_MISC, val);
 190
 191         /* Externally powered */
 192         pmic_reg_read(p, REG_CHARGE, &val);
 193         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
 194         pmic_reg_write(p, REG_CHARGE, val);
 195
 196         /* power up the system first */
 197         pmic_reg_write(p, REG_POWER_MISC, PWUP);
 198
 199         /* Set core voltage to 1.1V */
 200         pmic_reg_read(p, REG_SW_0, &val);
 201         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
 202         pmic_reg_write(p, REG_SW_0, val);
 203
 204         /* Setup VCC (SW2) to 1.25 */
 205         pmic_reg_read(p, REG_SW_1, &val);
 206         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 207         pmic_reg_write(p, REG_SW_1, val);
 208
 209         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 210         pmic_reg_read(p, REG_SW_2, &val);
 211         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 212         pmic_reg_write(p, REG_SW_2, val);
 213         udelay(50);
 214
 215         /* Raise the core frequency to 800MHz */
 216         writel(0x0, &mxc_ccm->cacrr);
 217
 218         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 219         /* Setup the switcher mode for SW1 & SW2*/
 220         pmic_reg_read(p, REG_SW_4, &val);
 221         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 222                 (SWMODE_MASK << SWMODE2_SHIFT)));
 223         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 224                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 225         pmic_reg_write(p, REG_SW_4, val);
 226
 227         /* Setup the switcher mode for SW3 & SW4 */
 228         pmic_reg_read(p, REG_SW_5, &val);
 229         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 230                 (SWMODE_MASK << SWMODE4_SHIFT)));
 231         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 232                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 233         pmic_reg_write(p, REG_SW_5, val);
 234
 235         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
 236         pmic_reg_read(p, REG_SETTING_0, &val);
 237         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 238         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
 239         pmic_reg_write(p, REG_SETTING_0, val);
 240
 241         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 242         pmic_reg_read(p, REG_SETTING_1, &val);
 243         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 244         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
 245         pmic_reg_write(p, REG_SETTING_1, val);
 246
 247         /* Configure VGEN3 and VCAM regulators to use external PNP */
 248         val = VGEN3CONFIG | VCAMCONFIG;
 249         pmic_reg_write(p, REG_MODE_1, val);
 250         udelay(200);
 251
 252         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 253         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 254                 VVIDEOEN | VAUDIOEN  | VSDEN;
 255         pmic_reg_write(p, REG_MODE_1, val);
 256
 257         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
 258                                                 NO_PAD_CTRL));
 259         gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
 260
 261         udelay(500);
 262
 263         gpio_set_value(IMX_GPIO_NR(2, 14), 1);
 264 }
 265
 266 #ifdef CONFIG_FSL_ESDHC_IMX
 267 int board_mmc_getcd(struct mmc *mmc)
 268 {
 269         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 270         int ret;
 271
 272         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
 273                                                 NO_PAD_CTRL));
 274         gpio_direction_input(IMX_GPIO_NR(1, 0));
 275         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
 276                                                 NO_PAD_CTRL));
 277         gpio_direction_input(IMX_GPIO_NR(1, 6));
 278
 279         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 280                 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
 281         else
 282                 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
 283
 284         return ret;
 285 }
 286
 287 int board_mmc_init(bd_t *bis)
 288 {
 289         static const iomux_v3_cfg_t sd1_pads[] = {
 290                 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
 291                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 292                 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
 293                         PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 294                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
 295                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 296                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
 297                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 298                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
 299                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 300                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
 301                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
 302                 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
 303                 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
 304         };
 305
 306         static const iomux_v3_cfg_t sd2_pads[] = {
 307                 NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
 308                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 309                 NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
 310                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 311                 NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
 312                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 313                 NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
 314                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 315                 NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
 316                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 317                 NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
 318                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 319                 NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
 320                 NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
 321         };
 322
 323         u32 index;
 324         int ret;
 325
 326         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 327         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 328
 329         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 330                         index++) {
 331                 switch (index) {
 332                 case 0:
 333                         imx_iomux_v3_setup_multiple_pads(sd1_pads,
 334                                                          ARRAY_SIZE(sd1_pads));
 335                         break;
 336                 case 1:
 337                         imx_iomux_v3_setup_multiple_pads(sd2_pads,
 338                                                          ARRAY_SIZE(sd2_pads));
 339                         break;
 340                 default:
 341                         printf("Warning: you configured more ESDHC controller"
 342                                 "(%d) as supported by the board(2)\n",
 343                                 CONFIG_SYS_FSL_ESDHC_NUM);
 344                         return -EINVAL;
 345                 }
 346                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 347                 if (ret)
 348                         return ret;
 349         }
 350         return 0;
 351 }
 352 #endif
 353
 354 int board_early_init_f(void)
 355 {
 356         setup_iomux_uart();
 357         setup_iomux_fec();
 358 #ifdef CONFIG_USB_EHCI_MX5
 359         setup_usb_h1();
 360 #endif
 361         setup_iomux_lcd();
 362
 363         return 0;
 364 }
 365
 366 int board_init(void)
 367 {
 368         /* address of boot parameters */
 369         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 370
 371         return 0;
 372 }
 373
 374 #ifdef CONFIG_BOARD_LATE_INIT
 375 int board_late_init(void)
 376 {
 377 #ifdef CONFIG_MXC_SPI
 378         setup_iomux_spi();
 379         power_init();
 380 #endif
 381
 382         return 0;
 383 }
 384 #endif
 385
 386 /*
 387  * Do not overwrite the console
 388  * Use always serial for U-Boot console
 389  */
 390 int overwrite_console(void)
 391 {
 392         return 1;
 393 }
 394
 395 int checkboard(void)
 396 {
 397         puts("Board: MX51EVK\n");
 398
 399         return 0;
 400 }