board/freescale/mx35pdk/mx35pdk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   4  *
   5  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <net.h>
  11 #include <asm/io.h>
  12 #include <linux/errno.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/iomux-mx35.h>
  17 #include <i2c.h>
  18 #include <power/pmic.h>
  19 #include <fsl_pmic.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <mc9sdz60.h>
  23 #include <mc13892.h>
  24 #include <linux/types.h>
  25 #include <asm/gpio.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <netdev.h>
  28 #include <asm/mach-types.h>
  29
  30 #ifndef CONFIG_BOARD_LATE_INIT
  31 #error "CONFIG_BOARD_LATE_INIT must be set for this board"
  32 #endif
  33
  34 #ifndef CONFIG_BOARD_EARLY_INIT_F
  35 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  36 #endif
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 int dram_init(void)
  41 {
  42         u32 size1, size2;
  43
  44         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  45         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  46
  47         gd->ram_size = size1 + size2;
  48
  49         return 0;
  50 }
  51
  52 int dram_init_banksize(void)
  53 {
  54         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  55         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  56
  57         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  58         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  59
  60         return 0;
  61 }
  62
  63 #define I2C_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
  64
  65 static void setup_iomux_i2c(void)
  66 {
  67         static const iomux_v3_cfg_t i2c1_pads[] = {
  68                 NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
  69                 NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
  70         };
  71
  72         /* setup pins for I2C1 */
  73         imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  74 }
  75
  76
  77 static void setup_iomux_spi(void)
  78 {
  79         static const iomux_v3_cfg_t spi_pads[] = {
  80                 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
  81                 MX35_PAD_CSPI1_MISO__CSPI1_MISO,
  82                 MX35_PAD_CSPI1_SS0__CSPI1_SS0,
  83                 MX35_PAD_CSPI1_SS1__CSPI1_SS1,
  84                 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
  85         };
  86
  87         imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
  88 }
  89
  90 #define USBOTG_IN_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
  91                                  PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  92 #define USBOTG_OUT_PAD_CTRL     (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  93
  94 static void setup_iomux_usbotg(void)
  95 {
  96         static const iomux_v3_cfg_t usbotg_pads[] = {
  97                 NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
  98                                 USBOTG_OUT_PAD_CTRL),
  99                 NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
 100                                 USBOTG_IN_PAD_CTRL),
 101         };
 102
 103         /* Set up pins for USBOTG. */
 104         imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
 105 }
 106
 107 #define FEC_PAD_CTRL    (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
 108
 109 static void setup_iomux_fec(void)
 110 {
 111         static const iomux_v3_cfg_t fec_pads[] = {
 112                 NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
 113                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 114                 NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
 115                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 116                 NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
 117                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 118                 NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
 119                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 120                 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
 121                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 122                 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
 123                 NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
 124                 NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
 125                 NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
 126                                         PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
 127                 NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
 128                 NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
 129                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 130                 NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
 131                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 132                 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
 133                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 134                 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
 135                 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
 136                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 137                 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
 138                 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
 139                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 140                 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
 141         };
 142
 143         /* setup pins for FEC */
 144         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 145 }
 146
 147 int board_early_init_f(void)
 148 {
 149         struct ccm_regs *ccm =
 150                 (struct ccm_regs *)IMX_CCM_BASE;
 151
 152         /* enable clocks */
 153         writel(readl(&ccm->cgr0) |
 154                 MXC_CCM_CGR0_EMI_MASK |
 155                 MXC_CCM_CGR0_EDIO_MASK |
 156                 MXC_CCM_CGR0_EPIT1_MASK,
 157                 &ccm->cgr0);
 158
 159         writel(readl(&ccm->cgr1) |
 160                 MXC_CCM_CGR1_FEC_MASK |
 161                 MXC_CCM_CGR1_GPIO1_MASK |
 162                 MXC_CCM_CGR1_GPIO2_MASK |
 163                 MXC_CCM_CGR1_GPIO3_MASK |
 164                 MXC_CCM_CGR1_I2C1_MASK |
 165                 MXC_CCM_CGR1_I2C2_MASK |
 166                 MXC_CCM_CGR1_IPU_MASK,
 167                 &ccm->cgr1);
 168
 169         /* Setup NAND */
 170         __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 171
 172         setup_iomux_i2c();
 173         setup_iomux_usbotg();
 174         setup_iomux_fec();
 175         setup_iomux_spi();
 176
 177         return 0;
 178 }
 179
 180 int board_init(void)
 181 {
 182         gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;    /* board id for linux */
 183         /* address of boot parameters */
 184         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 185
 186         return 0;
 187 }
 188
 189 static inline int pmic_detect(void)
 190 {
 191         unsigned int id;
 192         struct pmic *p = pmic_get("FSL_PMIC");
 193         if (!p)
 194                 return -ENODEV;
 195
 196         pmic_reg_read(p, REG_IDENTIFICATION, &id);
 197
 198         id = (id >> 6) & 0x7;
 199         if (id == 0x7)
 200                 return 1;
 201         return 0;
 202 }
 203
 204 u32 get_board_rev(void)
 205 {
 206         int rev;
 207
 208         rev = pmic_detect();
 209
 210         return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 211 }
 212
 213 int board_late_init(void)
 214 {
 215         u8 val;
 216         u32 pmic_val;
 217         struct pmic *p;
 218         int ret;
 219
 220         ret = pmic_init(I2C_0);
 221         if (ret)
 222                 return ret;
 223
 224         if (pmic_detect()) {
 225                 p = pmic_get("FSL_PMIC");
 226                 imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
 227
 228                 pmic_reg_read(p, REG_SETTING_0, &pmic_val);
 229                 pmic_reg_write(p, REG_SETTING_0,
 230                         pmic_val | VO_1_30V | VO_1_50V);
 231                 pmic_reg_read(p, REG_MODE_0, &pmic_val);
 232                 pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
 233
 234                 imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
 235
 236                 gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
 237         }
 238
 239         val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
 240         mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
 241         mdelay(200);
 242
 243         val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
 244         mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
 245         mdelay(200);
 246
 247         val |= 0x80;
 248         mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
 249
 250         /* Print board revision */
 251         printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
 252
 253         return 0;
 254 }
 255
 256 int board_eth_init(bd_t *bis)
 257 {
 258 #if defined(CONFIG_SMC911X)
 259         int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 260         if (rc)
 261                 return rc;
 262 #endif
 263         return cpu_eth_init(bis);
 264 }
 265
 266 #if defined(CONFIG_FSL_ESDHC_IMX)
 267
 268 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
 269
 270 int board_mmc_init(bd_t *bis)
 271 {
 272         static const iomux_v3_cfg_t sdhc1_pads[] = {
 273                 MX35_PAD_SD1_CMD__ESDHC1_CMD,
 274                 MX35_PAD_SD1_CLK__ESDHC1_CLK,
 275                 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
 276                 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
 277                 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
 278                 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 279         };
 280
 281         /* configure pins for SDHC1 only */
 282         imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 283
 284         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 285         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 286 }
 287
 288 int board_mmc_getcd(struct mmc *mmc)
 289 {
 290         return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
 291 }
 292 #endif