board/freescale/mx35pdk/mx35pdk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   4  *
   5  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <net.h>
  11 #include <asm/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/errno.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/iomux-mx35.h>
  18 #include <i2c.h>
  19 #include <power/pmic.h>
  20 #include <fsl_pmic.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <mc9sdz60.h>
  24 #include <mc13892.h>
  25 #include <linux/types.h>
  26 #include <asm/gpio.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <netdev.h>
  29 #include <asm/mach-types.h>
  30
  31 #ifndef CONFIG_BOARD_LATE_INIT
  32 #error "CONFIG_BOARD_LATE_INIT must be set for this board"
  33 #endif
  34
  35 #ifndef CONFIG_BOARD_EARLY_INIT_F
  36 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  37 #endif
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 int dram_init(void)
  42 {
  43         u32 size1, size2;
  44
  45         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  46         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  47
  48         gd->ram_size = size1 + size2;
  49
  50         return 0;
  51 }
  52
  53 int dram_init_banksize(void)
  54 {
  55         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  56         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  57
  58         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  59         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  60
  61         return 0;
  62 }
  63
  64 #define I2C_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
  65
  66 static void setup_iomux_i2c(void)
  67 {
  68         static const iomux_v3_cfg_t i2c1_pads[] = {
  69                 NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
  70                 NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
  71         };
  72
  73         /* setup pins for I2C1 */
  74         imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  75 }
  76
  77
  78 static void setup_iomux_spi(void)
  79 {
  80         static const iomux_v3_cfg_t spi_pads[] = {
  81                 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
  82                 MX35_PAD_CSPI1_MISO__CSPI1_MISO,
  83                 MX35_PAD_CSPI1_SS0__CSPI1_SS0,
  84                 MX35_PAD_CSPI1_SS1__CSPI1_SS1,
  85                 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
  86         };
  87
  88         imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
  89 }
  90
  91 #define USBOTG_IN_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
  92                                  PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  93 #define USBOTG_OUT_PAD_CTRL     (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  94
  95 static void setup_iomux_usbotg(void)
  96 {
  97         static const iomux_v3_cfg_t usbotg_pads[] = {
  98                 NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
  99                                 USBOTG_OUT_PAD_CTRL),
 100                 NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
 101                                 USBOTG_IN_PAD_CTRL),
 102         };
 103
 104         /* Set up pins for USBOTG. */
 105         imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
 106 }
 107
 108 #define FEC_PAD_CTRL    (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
 109
 110 static void setup_iomux_fec(void)
 111 {
 112         static const iomux_v3_cfg_t fec_pads[] = {
 113                 NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
 114                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 115                 NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
 116                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 117                 NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
 118                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 119                 NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
 120                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 121                 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
 122                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 123                 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
 124                 NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
 125                 NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
 126                 NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
 127                                         PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
 128                 NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
 129                 NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
 130                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 131                 NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
 132                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 133                 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
 134                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 135                 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
 136                 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
 137                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 138                 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
 139                 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
 140                                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
 141                 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
 142         };
 143
 144         /* setup pins for FEC */
 145         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 146 }
 147
 148 int board_early_init_f(void)
 149 {
 150         struct ccm_regs *ccm =
 151                 (struct ccm_regs *)IMX_CCM_BASE;
 152
 153         /* enable clocks */
 154         writel(readl(&ccm->cgr0) |
 155                 MXC_CCM_CGR0_EMI_MASK |
 156                 MXC_CCM_CGR0_EDIO_MASK |
 157                 MXC_CCM_CGR0_EPIT1_MASK,
 158                 &ccm->cgr0);
 159
 160         writel(readl(&ccm->cgr1) |
 161                 MXC_CCM_CGR1_FEC_MASK |
 162                 MXC_CCM_CGR1_GPIO1_MASK |
 163                 MXC_CCM_CGR1_GPIO2_MASK |
 164                 MXC_CCM_CGR1_GPIO3_MASK |
 165                 MXC_CCM_CGR1_I2C1_MASK |
 166                 MXC_CCM_CGR1_I2C2_MASK |
 167                 MXC_CCM_CGR1_IPU_MASK,
 168                 &ccm->cgr1);
 169
 170         /* Setup NAND */
 171         __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 172
 173         setup_iomux_i2c();
 174         setup_iomux_usbotg();
 175         setup_iomux_fec();
 176         setup_iomux_spi();
 177
 178         return 0;
 179 }
 180
 181 int board_init(void)
 182 {
 183         gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;    /* board id for linux */
 184         /* address of boot parameters */
 185         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 186
 187         return 0;
 188 }
 189
 190 static inline int pmic_detect(void)
 191 {
 192         unsigned int id;
 193         struct pmic *p = pmic_get("FSL_PMIC");
 194         if (!p)
 195                 return -ENODEV;
 196
 197         pmic_reg_read(p, REG_IDENTIFICATION, &id);
 198
 199         id = (id >> 6) & 0x7;
 200         if (id == 0x7)
 201                 return 1;
 202         return 0;
 203 }
 204
 205 u32 get_board_rev(void)
 206 {
 207         int rev;
 208
 209         rev = pmic_detect();
 210
 211         return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 212 }
 213
 214 int board_late_init(void)
 215 {
 216         u8 val;
 217         u32 pmic_val;
 218         struct pmic *p;
 219         int ret;
 220
 221         ret = pmic_init(I2C_0);
 222         if (ret)
 223                 return ret;
 224
 225         if (pmic_detect()) {
 226                 p = pmic_get("FSL_PMIC");
 227                 imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
 228
 229                 pmic_reg_read(p, REG_SETTING_0, &pmic_val);
 230                 pmic_reg_write(p, REG_SETTING_0,
 231                         pmic_val | VO_1_30V | VO_1_50V);
 232                 pmic_reg_read(p, REG_MODE_0, &pmic_val);
 233                 pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
 234
 235                 imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
 236
 237                 gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
 238         }
 239
 240         val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
 241         mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
 242         mdelay(200);
 243
 244         val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
 245         mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
 246         mdelay(200);
 247
 248         val |= 0x80;
 249         mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
 250
 251         /* Print board revision */
 252         printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
 253
 254         return 0;
 255 }
 256
 257 int board_eth_init(bd_t *bis)
 258 {
 259 #if defined(CONFIG_SMC911X)
 260         int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 261         if (rc)
 262                 return rc;
 263 #endif
 264         return cpu_eth_init(bis);
 265 }
 266
 267 #if defined(CONFIG_FSL_ESDHC_IMX)
 268
 269 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
 270
 271 int board_mmc_init(bd_t *bis)
 272 {
 273         static const iomux_v3_cfg_t sdhc1_pads[] = {
 274                 MX35_PAD_SD1_CMD__ESDHC1_CMD,
 275                 MX35_PAD_SD1_CLK__ESDHC1_CLK,
 276                 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
 277                 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
 278                 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
 279                 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 280         };
 281
 282         /* configure pins for SDHC1 only */
 283         imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 284
 285         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 286         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 287 }
 288
 289 int board_mmc_getcd(struct mmc *mmc)
 290 {
 291         return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
 292 }
 293 #endif