1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale MX28EVK board
5 * (C) Copyright 2011 Freescale Semiconductor, Inc.
7 * Author: Fabio Estevam <fabio.estevam@freescale.com>
10 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
11 * on behalf of DENX Software Engineering GmbH
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/iomux-mx28.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/sys_proto.h>
23 #include <linux/delay.h>
24 #include <linux/mii.h>
29 DECLARE_GLOBAL_DATA_PTR;
34 int board_early_init_f(void)
36 /* IO0 clock at 480MHz */
37 mxs_set_ioclk(MXC_IOCLK0, 480000);
38 /* IO1 clock at 480MHz */
39 mxs_set_ioclk(MXC_IOCLK1, 480000);
41 /* SSP0 clock at 96MHz */
42 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
43 /* SSP2 clock at 160MHz */
44 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
47 mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
48 mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
49 MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
50 gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
54 gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
56 /* Set contrast to maximum */
57 gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
64 return mxs_dram_init();
69 /* Adress of boot parameters */
70 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
76 static int mx28evk_mmc_wp(int id)
79 printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
83 return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
86 int board_mmc_init(bd_t *bis)
88 /* Configure WP as input */
89 gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
91 /* Configure MMC0 Power Enable */
92 gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
94 return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
100 int board_eth_init(bd_t *bis)
102 struct mxs_clkctrl_regs *clkctrl_regs =
103 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
104 struct eth_device *dev;
107 ret = cpu_eth_init(bis);
111 /* MX28EVK uses ENET_CLK PAD to drive FEC clock */
112 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
113 &clkctrl_regs->hw_clkctrl_enet);
116 gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
119 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
121 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
123 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
125 puts("FEC MXS: Unable to init FEC0\n");
129 ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
131 puts("FEC MXS: Unable to init FEC1\n");
135 dev = eth_get_dev_by_name("FEC0");
137 puts("FEC MXS: Unable to get FEC0 device entry\n");
141 dev = eth_get_dev_by_name("FEC1");
143 puts("FEC MXS: Unable to get FEC1 device entry\n");