board/freescale/mx25pdk/mx25pdk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2011 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <asm/io.h>
  11 #include <asm/gpio.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux-mx25.h>
  14 #include <asm/arch/clock.h>
  15 #include <mmc.h>
  16 #include <fsl_esdhc_imx.h>
  17 #include <i2c.h>
  18 #include <linux/delay.h>
  19 #include <power/pmic.h>
  20 #include <fsl_pmic.h>
  21 #include <mc34704.h>
  22
  23 #define FEC_RESET_B             IMX_GPIO_NR(4, 8)
  24 #define FEC_ENABLE_B            IMX_GPIO_NR(2, 3)
  25 #define CARD_DETECT             IMX_GPIO_NR(2, 1)
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_FSL_ESDHC_IMX
  30 struct fsl_esdhc_cfg esdhc_cfg[1] = {
  31         {IMX_MMC_SDHC1_BASE},
  32 };
  33 #endif
  34
  35 /*
  36  * FIXME: need to revisit this
  37  * The original code enabled PUE and 100-k pull-down without PKE, so the right
  38  * value here is likely:
  39  *      0 for no pull
  40  * or:
  41  *      PAD_CTL_PUS_100K_DOWN for 100-k pull-down
  42  */
  43 #define FEC_OUT_PAD_CTRL        0
  44
  45 #define I2C_PAD_CTRL            (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
  46                                  PAD_CTL_ODE)
  47
  48 static void mx25pdk_fec_init(void)
  49 {
  50         static const iomux_v3_cfg_t fec_pads[] = {
  51                 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
  52                 MX25_PAD_FEC_RX_DV__FEC_RX_DV,
  53                 MX25_PAD_FEC_RDATA0__FEC_RDATA0,
  54                 NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
  55                 NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
  56                 NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
  57                 MX25_PAD_FEC_MDIO__FEC_MDIO,
  58                 MX25_PAD_FEC_RDATA1__FEC_RDATA1,
  59                 NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
  60
  61                 NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
  62                 NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
  63         };
  64
  65         static const iomux_v3_cfg_t i2c_pads[] = {
  66                 NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
  67                 NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
  68         };
  69
  70         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  71
  72         /* Assert RESET and ENABLE low */
  73         gpio_direction_output(FEC_RESET_B, 0);
  74         gpio_direction_output(FEC_ENABLE_B, 0);
  75
  76         udelay(10);
  77
  78         /* Deassert RESET and ENABLE */
  79         gpio_set_value(FEC_RESET_B, 1);
  80         gpio_set_value(FEC_ENABLE_B, 1);
  81
  82         /* Setup I2C pins so that PMIC can turn on PHY supply */
  83         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
  84 }
  85
  86 int dram_init(void)
  87 {
  88         /* dram_init must store complete ramsize in gd->ram_size */
  89         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  90                                 PHYS_SDRAM_1_SIZE);
  91         return 0;
  92 }
  93
  94 /*
  95  * Set up input pins with hysteresis and 100-k pull-ups
  96  */
  97 #define UART1_IN_PAD_CTRL       (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
  98 /*
  99  * FIXME: need to revisit this
 100  * The original code enabled PUE and 100-k pull-down without PKE, so the right
 101  * value here is likely:
 102  *      0 for no pull
 103  * or:
 104  *      PAD_CTL_PUS_100K_DOWN for 100-k pull-down
 105  */
 106 #define UART1_OUT_PAD_CTRL      0
 107
 108 static void mx25pdk_uart1_init(void)
 109 {
 110         static const iomux_v3_cfg_t uart1_pads[] = {
 111                 NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
 112                 NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
 113                 NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
 114                 NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
 115         };
 116
 117         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 118 }
 119
 120 int board_early_init_f(void)
 121 {
 122         mx25pdk_uart1_init();
 123
 124         return 0;
 125 }
 126
 127 int board_init(void)
 128 {
 129         /* address of boot parameters */
 130         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 131
 132         return 0;
 133 }
 134
 135 int board_late_init(void)
 136 {
 137         struct pmic *p;
 138         int ret;
 139
 140         mx25pdk_fec_init();
 141
 142         ret = pmic_init(I2C_0);
 143         if (ret)
 144                 return ret;
 145
 146         p = pmic_get("FSL_PMIC");
 147         if (!p)
 148                 return -ENODEV;
 149
 150         /* Turn on Ethernet PHY and LCD supplies */
 151         pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
 152
 153         return 0;
 154 }
 155
 156 #ifdef CONFIG_FSL_ESDHC_IMX
 157 int board_mmc_getcd(struct mmc *mmc)
 158 {
 159         /* Set up the Card Detect pin. */
 160         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
 161
 162         gpio_direction_input(CARD_DETECT);
 163         return !gpio_get_value(CARD_DETECT);
 164 }
 165
 166 int board_mmc_init(bd_t *bis)
 167 {
 168         static const iomux_v3_cfg_t sdhc1_pads[] = {
 169                 NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
 170                 NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
 171                 NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
 172                 NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
 173                 NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
 174                 NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
 175         };
 176
 177         imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 178
 179         /*
 180          * Set the eSDHC1 PER clock to the maximum frequency lower than or equal
 181          * to 50 MHz that can be obtained, which requires to use UPLL as the
 182          * clock source. This actually gives 48 MHz.
 183          */
 184         imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000);
 185         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 186         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 187 }
 188 #endif
 189
 190 int checkboard(void)
 191 {
 192         puts("Board: MX25PDK\n");
 193
 194         return 0;
 195 }
 196
 197 /* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
 198 void lowlevel_init(void) {}