1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
12 #include <asm/processor.h>
13 #include <asm/immap_86xx.h>
14 #include <asm/fsl_pci.h>
15 #include <fsl_ddr_sdram.h>
16 #include <asm/fsl_serdes.h>
19 #include <linux/delay.h>
20 #include <linux/libfdt.h>
21 #include <fdt_support.h>
22 #include <spd_sdram.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 void sdram_init(void);
28 phys_size_t fixed_sdram(void);
29 int mpc8610hpcd_diu_init(void);
32 /* called before any console output */
33 int board_early_init_f(void)
35 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
36 volatile ccsr_gur_t *gur = &immap->im_gur;
38 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
46 u8 *pixis_base = (u8 *)PIXIS_BASE;
48 /*Do not use 8259PIC*/
49 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
50 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
52 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
53 version = in_8(pixis_base + PIXIS_PVER);
55 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
56 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
59 /* Using this for DIU init before the driver in linux takes over
60 * Enable the TFP410 Encoder (I2C address 0x38)
64 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
65 /* Verify if enabled */
67 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
68 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
71 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
72 /* Verify if enabled */
74 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
75 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
82 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
83 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
84 u8 *pixis_base = (u8 *)PIXIS_BASE;
86 printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
87 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
88 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
89 in_8(pixis_base + PIXIS_PVER));
92 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
93 * bank and LBMAP=00 is the alternate bank. However, the pixis
94 * altbank code can only set bits, not clear them, so we treat 00 as
95 * the normal bank and 11 as the alternate.
97 switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
99 puts("vBank: Standard\n");
108 puts("vBank: Alternate\n");
112 mcm->abcr |= 0x00010000; /* 0 */
113 mcm->hpmr3 = 0x80000008; /* 4c */
126 phys_size_t dram_size = 0;
128 #if defined(CONFIG_SPD_EEPROM)
129 dram_size = fsl_ddr_sdram();
131 dram_size = fixed_sdram();
134 setup_ddr_bat(dram_size);
137 gd->ram_size = dram_size;
143 #if !defined(CONFIG_SPD_EEPROM)
145 * Fixed sdram init -- doesn't use serial presence detect.
148 phys_size_t fixed_sdram(void)
150 #if !defined(CONFIG_SYS_RAMBOOT)
151 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
152 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
155 ddr->cs0_bnds = 0x0000001f;
156 ddr->cs0_config = 0x80010202;
158 ddr->timing_cfg_3 = 0x00000000;
159 ddr->timing_cfg_0 = 0x00260802;
160 ddr->timing_cfg_1 = 0x3935d322;
161 ddr->timing_cfg_2 = 0x14904cc8;
162 ddr->sdram_mode = 0x00480432;
163 ddr->sdram_mode_2 = 0x00000000;
164 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
165 ddr->sdram_data_init = 0xDEADBEEF;
166 ddr->sdram_clk_cntl = 0x03800000;
167 ddr->sdram_cfg_2 = 0x04400010;
169 #if defined(CONFIG_DDR_ECC)
170 ddr->err_int_en = 0x0000000d;
171 ddr->err_disable = 0x00000000;
172 ddr->err_sbe = 0x00010000;
178 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
181 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
183 debug("DDR - 1st controller: memory initializing\n");
185 * Poll until memory is initialized.
186 * 512 Meg at 400 might hit this 200 times or so.
188 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
191 debug("DDR: memory initialized\n\n");
196 return 512 * 1024 * 1024;
198 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
203 #if defined(CONFIG_PCI)
205 * Initialize PCI Devices, report devices found.
208 #ifndef CONFIG_PCI_PNP
209 static struct pci_config_table pci_fsl86xxads_config_table[] = {
210 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
211 PCI_IDSEL_NUMBER, PCI_ANY_ID,
212 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
214 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
220 static struct pci_controller pci1_hose;
221 #endif /* CONFIG_PCI */
223 void pci_init_board(void)
225 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
226 volatile ccsr_gur_t *gur = &immap->im_gur;
227 struct fsl_pci_info pci_info;
229 int first_free_busno;
232 devdisr = in_be32(&gur->devdisr);
234 first_free_busno = fsl_pcie_init_board(0);
237 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
238 SET_STD_PCI_INFO(pci_info, 1);
239 set_next_law(pci_info.mem_phys,
240 law_size_bits(pci_info.mem_size), pci_info.law);
241 set_next_law(pci_info.io_phys,
242 law_size_bits(pci_info.io_size), pci_info.law);
244 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
245 printf("PCI: connected to PCI slots as %s" \
246 " (base address %lx)\n",
247 pci_agent ? "Agent" : "Host",
249 #ifndef CONFIG_PCI_PNP
250 pci1_hose.config_table = pci_mpc86xxcts_config_table;
252 first_free_busno = fsl_pci_init_port(&pci_info,
253 &pci1_hose, first_free_busno);
255 printf("PCI: disabled\n");
260 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
263 fsl_pcie_init_board(first_free_busno);
266 #if defined(CONFIG_OF_BOARD_SETUP)
267 int ft_board_setup(void *blob, bd_t *bd)
269 ft_cpu_setup(blob, bd);
279 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
283 get_board_sys_clk(ulong dummy)
287 u8 *pixis_base = (u8 *)PIXIS_BASE;
289 i = in_8(pixis_base + PIXIS_SPD);
322 int board_eth_init(bd_t *bis)
324 return pci_eth_init(bis);
327 void board_reset(void)
329 u8 *pixis_base = (u8 *)PIXIS_BASE;
331 out_8(pixis_base + PIXIS_RST, 0);