1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
14 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_pci.h>
19 #include <fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
23 #include <linux/delay.h>
24 #include <linux/libfdt.h>
25 #include <fdt_support.h>
30 #include "../common/sgmii_riser.h"
35 u8 *pixis_base = (u8 *)PIXIS_BASE;
37 printf("Board: MPC8572DS Sys ID: 0x%02x, "
38 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
39 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
40 in_8(pixis_base + PIXIS_PVER));
42 vboot = in_8(pixis_base + PIXIS_VBOOT);
43 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
44 case PIXIS_VBOOT_LBMAP_NOR0:
47 case PIXIS_VBOOT_LBMAP_PJET:
50 case PIXIS_VBOOT_LBMAP_NAND:
53 case PIXIS_VBOOT_LBMAP_NOR1:
62 #if !defined(CONFIG_SPD_EEPROM)
64 * Fixed sdram init -- doesn't use serial presence detect.
67 phys_size_t fixed_sdram (void)
69 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
70 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
73 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
74 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
76 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
77 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
78 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
79 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
80 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
81 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
82 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
83 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
84 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
85 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
87 #if defined (CONFIG_DDR_ECC)
88 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
89 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
90 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
96 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
98 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
100 debug("DDR - 1st controller: memory initializing\n");
102 * Poll until memory is initialized.
103 * 512 Meg at 400 might hit this 200 times or so.
105 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
108 debug("DDR: memory initialized\n\n");
113 return 512 * 1024 * 1024;
119 void pci_init_board(void)
121 struct pci_controller *hose;
123 fsl_pcie_init_board(0);
125 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
129 u8 uli_busno = hose->first_busno + 2;
132 * Activate ULI1575 legacy chip by performing a fake
133 * memory access. Needed to make ULI RTC work.
134 * Device 1d has the first on-board memory BAR.
136 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
137 PCI_BASE_ADDRESS_1, &temp32);
139 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
140 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
142 debug(" uli1572 read to %p\n", p);
149 int board_early_init_r(void)
151 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
152 int flash_esel = find_tlb_idx((void *)flashbase, 1);
155 * Remap Boot flash + PROMJET region to caching-inhibited
156 * so that flash can be erased properly.
159 /* Flush d-cache and invalidate i-cache of any FLASH data */
163 if (flash_esel == -1) {
164 /* very unlikely unless something is messed up */
165 puts("Error: Could not find TLB for FLASH BASE\n");
166 flash_esel = 2; /* give our best effort to continue */
168 /* invalidate existing TLB entry for flash + promjet */
169 disable_tlb(flash_esel);
172 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
173 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
174 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
179 int board_eth_init(bd_t *bis)
181 #ifdef CONFIG_TSEC_ENET
182 struct fsl_pq_mdio_info mdio_info;
183 struct tsec_info_struct tsec_info[4];
187 SET_STD_TSEC_INFO(tsec_info[num], 1);
188 if (is_serdes_configured(SGMII_TSEC1)) {
189 puts("eTSEC1 is in sgmii mode.\n");
190 tsec_info[num].flags |= TSEC_SGMII;
195 SET_STD_TSEC_INFO(tsec_info[num], 2);
196 if (is_serdes_configured(SGMII_TSEC2)) {
197 puts("eTSEC2 is in sgmii mode.\n");
198 tsec_info[num].flags |= TSEC_SGMII;
203 SET_STD_TSEC_INFO(tsec_info[num], 3);
204 if (is_serdes_configured(SGMII_TSEC3)) {
205 puts("eTSEC3 is in sgmii mode.\n");
206 tsec_info[num].flags |= TSEC_SGMII;
211 SET_STD_TSEC_INFO(tsec_info[num], 4);
212 if (is_serdes_configured(SGMII_TSEC4)) {
213 puts("eTSEC4 is in sgmii mode.\n");
214 tsec_info[num].flags |= TSEC_SGMII;
220 printf("No TSECs initialized\n");
225 #ifdef CONFIG_FSL_SGMII_RISER
226 fsl_sgmii_riser_init(tsec_info, num);
229 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
230 mdio_info.name = DEFAULT_MII_NAME;
231 fsl_pq_mdio_init(bis, &mdio_info);
233 tsec_eth_init(bis, tsec_info, num);
236 return pci_eth_init(bis);
239 #if defined(CONFIG_OF_BOARD_SETUP)
240 int ft_board_setup(void *blob, bd_t *bd)
245 ft_cpu_setup(blob, bd);
247 base = env_get_bootm_low();
248 size = env_get_bootm_size();
250 fdt_fixup_memory(blob, (u64)base, (u64)size);
254 #ifdef CONFIG_FSL_SGMII_RISER
255 fsl_sgmii_riser_fdt_fixup(blob);