1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
14 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_pci.h>
19 #include <fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
23 #include <linux/libfdt.h>
24 #include <fdt_support.h>
29 #include "../common/sgmii_riser.h"
34 u8 *pixis_base = (u8 *)PIXIS_BASE;
36 printf("Board: MPC8572DS Sys ID: 0x%02x, "
37 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
38 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
39 in_8(pixis_base + PIXIS_PVER));
41 vboot = in_8(pixis_base + PIXIS_VBOOT);
42 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
43 case PIXIS_VBOOT_LBMAP_NOR0:
46 case PIXIS_VBOOT_LBMAP_PJET:
49 case PIXIS_VBOOT_LBMAP_NAND:
52 case PIXIS_VBOOT_LBMAP_NOR1:
61 #if !defined(CONFIG_SPD_EEPROM)
63 * Fixed sdram init -- doesn't use serial presence detect.
66 phys_size_t fixed_sdram (void)
68 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
69 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
72 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
73 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
75 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
76 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
77 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
78 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
79 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
80 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
81 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
82 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
83 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
84 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
86 #if defined (CONFIG_DDR_ECC)
87 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
88 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
89 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
95 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
97 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
99 debug("DDR - 1st controller: memory initializing\n");
101 * Poll until memory is initialized.
102 * 512 Meg at 400 might hit this 200 times or so.
104 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
107 debug("DDR: memory initialized\n\n");
112 return 512 * 1024 * 1024;
118 void pci_init_board(void)
120 struct pci_controller *hose;
122 fsl_pcie_init_board(0);
124 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
128 u8 uli_busno = hose->first_busno + 2;
131 * Activate ULI1575 legacy chip by performing a fake
132 * memory access. Needed to make ULI RTC work.
133 * Device 1d has the first on-board memory BAR.
135 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
136 PCI_BASE_ADDRESS_1, &temp32);
138 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
139 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
141 debug(" uli1572 read to %p\n", p);
148 int board_early_init_r(void)
150 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
151 int flash_esel = find_tlb_idx((void *)flashbase, 1);
154 * Remap Boot flash + PROMJET region to caching-inhibited
155 * so that flash can be erased properly.
158 /* Flush d-cache and invalidate i-cache of any FLASH data */
162 if (flash_esel == -1) {
163 /* very unlikely unless something is messed up */
164 puts("Error: Could not find TLB for FLASH BASE\n");
165 flash_esel = 2; /* give our best effort to continue */
167 /* invalidate existing TLB entry for flash + promjet */
168 disable_tlb(flash_esel);
171 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
172 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
173 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
178 int board_eth_init(bd_t *bis)
180 #ifdef CONFIG_TSEC_ENET
181 struct fsl_pq_mdio_info mdio_info;
182 struct tsec_info_struct tsec_info[4];
186 SET_STD_TSEC_INFO(tsec_info[num], 1);
187 if (is_serdes_configured(SGMII_TSEC1)) {
188 puts("eTSEC1 is in sgmii mode.\n");
189 tsec_info[num].flags |= TSEC_SGMII;
194 SET_STD_TSEC_INFO(tsec_info[num], 2);
195 if (is_serdes_configured(SGMII_TSEC2)) {
196 puts("eTSEC2 is in sgmii mode.\n");
197 tsec_info[num].flags |= TSEC_SGMII;
202 SET_STD_TSEC_INFO(tsec_info[num], 3);
203 if (is_serdes_configured(SGMII_TSEC3)) {
204 puts("eTSEC3 is in sgmii mode.\n");
205 tsec_info[num].flags |= TSEC_SGMII;
210 SET_STD_TSEC_INFO(tsec_info[num], 4);
211 if (is_serdes_configured(SGMII_TSEC4)) {
212 puts("eTSEC4 is in sgmii mode.\n");
213 tsec_info[num].flags |= TSEC_SGMII;
219 printf("No TSECs initialized\n");
224 #ifdef CONFIG_FSL_SGMII_RISER
225 fsl_sgmii_riser_init(tsec_info, num);
228 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
229 mdio_info.name = DEFAULT_MII_NAME;
230 fsl_pq_mdio_init(bis, &mdio_info);
232 tsec_eth_init(bis, tsec_info, num);
235 return pci_eth_init(bis);
238 #if defined(CONFIG_OF_BOARD_SETUP)
239 int ft_board_setup(void *blob, bd_t *bd)
244 ft_cpu_setup(blob, bd);
246 base = env_get_bootm_low();
247 size = env_get_bootm_size();
249 fdt_fixup_memory(blob, (u64)base, (u64)size);
253 #ifdef CONFIG_FSL_SGMII_RISER
254 fsl_sgmii_riser_fdt_fixup(blob);